公开(公告)号：US08228710B2

公开(公告)日：2012-07-24

申请号：US12715231

申请日：2010-03-01

申请人： Kenji Tsuchida

发明人： Kenji Tsuchida

IPC分类号： G11C11/00

CPC分类号： H01L27/24 ,  G11C8/08 ,  G11C8/10 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  H01L27/228

摘要： A resistance change memory device includes memory cells including two transistors connected in parallel between a first node and a connecting node and a variable resistance element whose one end is connected to the connecting node. The first node of each memory cell and a second node, which is the other end of the variable resistance element of the memory cell, are connected to different bit lines. The first node of a one memory cell and the first node of another memory cell which is adjacent on a first side along the second axis to the one memory are connected to the same bit line. The second node of the one memory cell and the second node of still another memory cell which is adjacent on a second side along the second axis to the one memory cell are connected to the same bit line.

摘要翻译： 电阻变化存储器件包括：存储单元，包括并联连接在第一节点和连接节点之间的两个晶体管，以及可变电阻元件，其一端连接到连接节点。 每个存储单元的第一节点和作为存储单元的可变电阻元件的另一端的第二节点连接到不同的位线。 一个存储单元的第一个节点和另一个存储单元的第一个节点连接到相同的位线，该存储单元的第一个边沿第二个轴与第一个轴相邻。 一个存储单元的第二个节点和另一个存储单元的另一个存储单元的第二个节点连接到相同的位线。

公开(公告)号：US20120069639A1

公开(公告)日：2012-03-22

申请号：US13228255

申请日：2011-09-08

申请人： Katsuhiko Hoya ,  Kenji Tsuchida

发明人： Katsuhiko Hoya ,  Kenji Tsuchida

IPC分类号： G11C11/00

CPC分类号： G11C11/1693 ,  G11C11/1675

摘要： A memory according to an embodiment includes bit lines, word lines, source lines, magnetic tunnel junction elements and transistors that are serially connected between the bit lines and the source lines, respectively, and a sense amplifier that detects data stored in the magnetic tunnel junction elements. The semiconductor storage device includes multiplexers between the bit lines and the sense amplifier in order to select one of the bit lines to be connected to the sense amplifier, and write amplifiers that are located corresponding to memory cell blocks each of which includes memory cells each including the magnetic tunnel junction element and the transistor and are connected to the bit lines or connected via the multiplexers to the bit lines. To write data, the sense amplifier applies a write voltage to the bit lines and then the write amplifiers hold the write voltage.

摘要翻译： 根据实施例的存储器分别包括位线和源极线之间串联连接的位线，字线，源极线，磁性隧道结元件和晶体管，以及检测放大器，其检测存储在磁性隧道结中的数据 元素。 半导体存储装置包括位线和读出放大器之间的多路复用器，以便选择要连接到读出放大器的位线之一，以及对应于存储单元块的写入放大器，每个存储单元块包括各自包括 磁隧道结元件和晶体管，并且连接到位线或经由多路复用器连接到位线。 为了写入数据，读出放大器向位线施加写入电压，然后写入放大器保持写入电压。

公开(公告)号：US20100046274A1

公开(公告)日：2010-02-25

申请号：US12543793

申请日：2009-08-19

申请人： Kenji TSUCHIDA ,  Yoshihiro UEDA

发明人： Kenji TSUCHIDA ,  Yoshihiro UEDA

IPC分类号： G11C11/00 ,  G11C7/02 ,  G11C8/00

CPC分类号： G11C11/1673 ,  G11C11/1659 ,  G11C11/1675

摘要： A resistance change memory includes two memory cell arrays each including a plurality of memory cells, the memory cells including variable resistive elements, two reference cell arrays provided to correspond to the two memory cell arrays, respectively, and each including a plurality of reference cells, the reference cells having a reference value, and a sense amplifier shared by the two memory cell arrays and detecting data in an accessed memory cell by use of a reference cell array corresponding to a second memory cell array different from a first memory cell array including the accessed memory cell. In reading the data, a particular reference cell in one reference cell array is always activated for an address space based on one memory cell array as a unit.

摘要翻译： 电阻变化存储器包括两个存储单元阵列，每个存储单元阵列包括多个存储单元，存储单元包括可变电阻元件，分别提供给两个存储单元阵列的两个参考单元阵列，每个参考单元阵列包括多个参考单元， 所述参考单元具有参考值，以及由所述两个存储单元阵列共享的读出放大器，并且通过使用与包括所述存储单元阵列的第一存储单元阵列不同的第二存储单元阵列对应的参考单元阵列来检测所访问的存储器单元中的数据 存取存储单元 在读取数据时，一个参考单元阵列中的特定参考单元总是基于一个存储单元阵列作为单元而被激活用于地址空间。

公开(公告)号：US20070279963A1

公开(公告)日：2007-12-06

申请号：US11673206

申请日：2007-02-09

申请人： Kenji TSUCHIDA ,  Yoshihiro UEDA

发明人： Kenji TSUCHIDA ,  Yoshihiro UEDA

IPC分类号： G11C11/00

CPC分类号： G11C11/1657 ,  G11C11/1655

摘要： The first memory cell in even columns is composed of a first resistance change element one end of which is connected to a first bit line, and first and second FETs connected in parallel between the other end of the first resistance change element and a second bit line. The second memory cell in odd columns is composed of a second resistance change element one end of which is connected to a third bit line, and third and fourth FETs connected in parallel between the other end of the second resistance change element and a fourth bit line. A gate of the first FET is connected to the first word line. Gates of the second and third FETs are connected together to the second word line. A gate of the fourth FET is connected to the third word line.

摘要翻译： 偶数列中的第一存储单元由第一电阻变化元件组成，其一端连接到第一位线，并且第一和第二FET并联连接在第一电阻变化元件的另一端和第二位线 。 奇数列中的第二存储单元由第二电阻变化元件组成，其一端连接到第三位线，第三和第四FET并联连接在第二电阻变化元件的另一端和第四位线之间 。 第一个FET的栅极连接到第一个字线。 第二和第三FET的栅极连接在一起到第二字线。 第四FET的栅极连接到第三字线。

公开(公告)号：US07116598B2

公开(公告)日：2006-10-03

申请号：US11084037

申请日：2005-03-21

申请人： Yuui Shimizu ,  Yoshihisa Iwata ,  Kenji Tsuchida

发明人： Yuui Shimizu ,  Yoshihisa Iwata ,  Kenji Tsuchida

IPC分类号： G11C7/02

CPC分类号： G11C11/16 ,  G11C7/062 ,  G11C7/14

摘要： A semiconductor memory comprises a memory cell, a pair of reference cells for use in generation of a reference electric potential, a first read circuit which compares a read electric potential obtained from the memory cell with the reference electric potential and determines data in the memory cell, a second read circuit which detects a state of the pair of reference cells and outputs a detection signal indicating the state of the pair of reference cells, and a control circuit which controls a write operation for the pair of reference cells based on the detection signal.

公开(公告)号：US20050213401A1

公开(公告)日：2005-09-29

申请号：US10952721

申请日：2004-09-30

申请人： Yuui Shimizu ,  Kenji Tsuchida

发明人： Yuui Shimizu ,  Kenji Tsuchida

IPC分类号： G11C11/15 ,  G11C11/14 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

CPC分类号： G11C29/816 ,  G11C11/16 ,  G11C29/808

摘要： A semiconductor integrated circuit device includes a main memory cell array, redundant memory cell array, write current source, a common node connected to the write current source, a first selector connected between the common node and one-side ends of main write wirings and a second selector connected between the common node and one-side ends of redundant write wirings. The redundant memory cell array is arranged in a position apart from the main memory cell array and the write current source is commonly used by the main memory cell array and redundant memory cell array via the common node.

摘要翻译： 一种半导体集成电路装置，包括主存储单元阵列，冗余存储单元阵列，写入电流源，连接到写入电流源的公共节点，连接在公共节点和主要写入配线的一侧端部之间的第一选择器，以及 第二选择器连接在公共节点和冗余写配线的一端之间。 冗余存储单元阵列布置在远离主存储单元阵列的位置，并且写入电流源通过主存储单元阵列和冗余存储单元阵列经由公共节点共同使用。

公开(公告)号：US20050180204A1

公开(公告)日：2005-08-18

申请号：US10855497

申请日：2004-05-28

申请人： Ryousuke Takizawa ,  Kenji Tsuchida ,  Yoshihisa Iwata ,  Tsuneo Inaba

发明人： Ryousuke Takizawa ,  Kenji Tsuchida ,  Yoshihisa Iwata ,  Tsuneo Inaba

IPC分类号： G11C11/15 ,  G11C11/14

CPC分类号： G11C11/14

摘要： A memory cell of a magnetic memory device has an MTJ element and one end of the memory cell is selectively electrically connected to a ground potential line. A first bit line is electrically connected to the other end of the memory cell. A sense amplifier amplifies a difference in potential between the first bit line and a second bit line complementary to the first bit line so that the difference is equal to or larger than a difference between an internal power potential and a ground potential. A connection circuit disconnects the MTJ element from an electric connection between the ground potential line and the sense amplifier.

摘要翻译： 磁存储器件的存储单元具有MTJ元件，并且存储单元的一端选择性地电连接到地电位线。 第一位线电连接到存储器单元的另一端。 读出放大器放大与第一位线互补的第一位线和第二位线之间的电位差，使得差值等于或大于内部功率电位和接地电位之间的差。 连接电路将MTJ元件与地电位线和读出放大器之间的电气连接断开。

公开(公告)号：US06661734B2

公开(公告)日：2003-12-09

申请号：US10193223

申请日：2002-07-12

申请人： Tsuneo Inaba ,  Kenji Tsuchida

发明人： Tsuneo Inaba ,  Kenji Tsuchida

IPC分类号： G11C800

CPC分类号： G11C8/08

摘要： A semiconductor memory device is disclosed, in which a first word drive line control circuit which supplies a word drive voltage corresponding to the decode output of the decoding circuit to the first word drive line, and has a first reset circuit which resets the first word drive line to a first potential when a first control signal is activated and a second reset circuit which resets the first word drive line to a second potential when a second control signal is activated, and a two-stage reset control circuit which controls changeover from the activated state of the first control signal to the activated state of the second control signal on the basis of the potential of the first word drive line to change the potential of the first word drive line in two stages.

摘要翻译： 公开了一种半导体存储器件，其中第一字驱动线控制电路将对应于解码电路的解码输出的字驱动电压提供给第一字驱动线，并且具有复位第一字驱动器的第一复位电路 当第一控制信号被激活时，将第一电位线切换到第一电位;以及第二复位电路，其在第二控制信号被激活时将第一字驱动线复位到第二电位;以及两级复位控制电路，其控制从激活的第二控制信号的转换 基于第一字驱动线的电位将第一控制信号的状态转换为第二控制信号的激活状态，以改变第一字驱动线的电位两级。

公开(公告)号：US06480423B2

公开(公告)日：2002-11-12

申请号：US09873313

申请日：2001-06-05

申请人： Haruki Toda ,  Kenji Tsuchida ,  Hitoshi Kuyama

发明人： Haruki Toda ,  Kenji Tsuchida ,  Hitoshi Kuyama

IPC分类号： G11C700

CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C11/4087

摘要： A high-speed clock-synchronous memory device is provided with a sense amplifier S/A shared by and between cell arrays, and a cell array controller unit CNTRLi, wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between tow successive commands, regarding some of the address bits configuring an access address, the device judges whether the current access is made within the same cell array as the preceding access, between the neighboring cell arrays, or between remote cell arrays. According to the judgment, suitable command cycle is applied. At this time, the command cycle satisfies the relationship: S≧N≧F.

摘要翻译： 高速时钟同步存储装置设置有由单元阵列之间和单元阵列之间共享的读出放大器S / A和单元阵列控制器单元CNTRLi，其中与时钟同步的数据/命令的输入和输出访问命令提供所有 同时地址数据位（行和列）。 通过确认在两个连续命令之间观察到的位的改变，关于配置访问地址的一些地址位，设备判断当前访问是在与先前的访问相同的单元阵列之间，相邻单元阵列之间，还是在 远程单元阵列。 根据判断，应用适当的命令循环。 此时，命令循环满足关系：S> = N> = F。

公开(公告)号：US06452860B2

公开(公告)日：2002-09-17

申请号：US09871646

申请日：2001-06-04

申请人： Masaharu Wada ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Atsushi Takeuchi ,  Toshimi Ikeda ,  Kuninori Kawabata

发明人： Masaharu Wada ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Atsushi Takeuchi ,  Toshimi Ikeda ,  Kuninori Kawabata

IPC分类号： G11C800

CPC分类号： G11C5/063

摘要： A semiconductor memory device has a segment type word line structure and comprises a plurality of main word lines and a plurality of sub word lines which are arranged at different levels. The semiconductor memory device is provided with a memory cell array divided into a plurality of cell array blocks. A plurality of sub row decoder areas, each for selecting one of the sub word lines, are defined between the cell array blocks. A plurality of first metal wiring lines formed by use of the same wiring layer as the main word lines are provided. The first metal wiring lines pass across the sub row decoder areas and the cell array blocks.

摘要翻译： 半导体存储器件具有段类型的字线结构，并且包括多个主字线和排列在不同电平的多个子字线。 半导体存储器件设置有分成多个单元阵列块的存储单元阵列。 在单元阵列块之间定义多个用于选择一个子字线的子行解码器区域。 提供了通过使用与主字线相同的布线层形成的多个第一金属布线。 第一金属布线穿过子行解码器区域和单元阵列块。