公开(公告)号：US5933380A

公开(公告)日：1999-08-03

申请号：US871587

申请日：1997-06-09

申请人： Kenji Tsuchida ,  Yukihito Oowaki ,  Kazunori Ohuchi

发明人： Kenji Tsuchida ,  Yukihito Oowaki ,  Kazunori Ohuchi

IPC分类号： H01L21/8242 ,  G11C7/18 ,  G11C11/401 ,  H01L27/108 ,  G11C7/02

CPC分类号： G11C7/18

摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells, the memory cell array being divided into a plurality of blocks, a plurality first bitlines arranged in each of the blocks, the plurality of first bitlines forming a plurality of first bitline pair each having a folded bitline structure with two of the plurality of first bitlines as a basic unit, a plurality second bitlines arranged to correspond to at least one of the blocks and formed above the first bitlines, the plurality of second bitlines forming a plurality of second bitline pair each having a folded bitline structure with two of the plurality of second bitlines as a basic unit, a plurality of sense amplifier circuits, arranged to correspond to the plurality of second bitline pairs, for detecting and amplifying information stored in the memory cells, and a plurality of select circuits for selecting one of two of first bitlines included in one of the plurality of first bitline pairs to selectively connect a selected first bitline with one of two of second bitlines included in one of the plurality of second bitline pairs.

摘要翻译： 半导体存储器件包括具有多个存储单元的存储单元阵列，该存储单元阵列被划分为多个块，多个第一位线布置在每个块中，多个第一位线形成多个第一位线 所述多个第二位线具有折叠的位线结构，其中所述多个第一位线中的两个作为基本单元，多个第二位线被布置成对应于所述块中的至少一个并且形成在所述第一位线上方，所述多个第二位线形成多个 第二位线对，其具有折叠的位线结构，其中所述多个第二位线中的两个作为基本单元;多个读出放大器电路，被布置为对应于所述多个第二位线对，用于检测和放大存储在所述存储器单元中的信息 以及多个选择电路，用于选择包括在所述多个第一位线对之一中的两个第一位线之一至s 选择性地将所选择的第一位线与包括在所述多个第二位线对之一中的第二位线之一中的一个位线连接。

公开(公告)号：US06327654B1

公开(公告)日：2001-12-04

申请号：US09151774

申请日：1998-09-11

申请人： Yukihito Oowaki ,  Hiroshige Fujii ,  Hideo Shimizu ,  Takehisa Kato ,  Naoki Endo ,  Atsushi Masuda ,  Hiroaki Nishi ,  Kazunori Ohuchi ,  Masatoshi Sekine

发明人： Yukihito Oowaki ,  Hiroshige Fujii ,  Hideo Shimizu ,  Takehisa Kato ,  Naoki Endo ,  Atsushi Masuda ,  Hiroaki Nishi ,  Kazunori Ohuchi ,  Masatoshi Sekine

IPC分类号： G06F1130

CPC分类号： G06F21/72 ,  H04L9/0625 ,  H04L2209/08 ,  H04L2209/122 ,  H04L2209/125

摘要： A semiconductor integrated circuit for cryptographic process according to the present invention, comprises a randomizing unit for randomizing first input data which is one of two divided parts of input data based on configuration information to identify an algorithm in randomizing process, a function F portion for receiving data which have been subjected to the randomizing process and then applying coding process to the data, and an exclusive logical sum circuit for receiving second input data which is other of two divided parts of the input data and output data from the function F portion and then outputting an exclusive logical sum of the second input data and the output data.

摘要翻译： 根据本发明的用于密码处理的半导体集成电路包括：随机化单元，用于基于配置信息随机化作为输入数据的两个分割部分之一的第一输入数据，以识别随机化过程中的算法;函数F部分，用于接收 已经经过随机化处理然后对数据进行编码处理的数据，以及用于接收作为输入数据的两个分割部分中的另外两个部分的第二输入数据和来自功能F部分的输出数据的异或逻辑和电路， 输出第二输入数据和输出数据的异或逻辑和。

公开(公告)号：US06349395B2

公开(公告)日：2002-02-19

申请号：US09154027

申请日：1998-09-16

申请人： Kazunori Ohuchi ,  Masako Yoshida ,  Yukihito Oowaki ,  Hiroshige Fujii ,  Masatoshi Sekine

发明人： Kazunori Ohuchi ,  Masako Yoshida ,  Yukihito Oowaki ,  Hiroshige Fujii ,  Masatoshi Sekine

IPC分类号： G01R3128

CPC分类号： G01R31/318516

摘要： An integrated circuit has configurable logic blocks that are reconfigurable, hard-wired logic blocks that carry out fixed operations, and a memory. The memory stores configuration data for configuring the configurable logic blocks, block-connection data for determining connections between the configurable and hard-wired logic blocks, and partial-circuit-connection data for determining connections between partial circuits each of which consists of logic blocks selected among the configurable and hard-wired logic blocks. These pieces of data are shared by the logic blocks to reduce the number of memories in the integrated circuit and improve the packaging density of the integrated circuit.

摘要翻译： 集成电路具有可配置逻辑块，其是可重新配置的，执行固定操作的硬连线逻辑块，以及存储器。 存储器存储用于配置可配置逻辑块的配置数据，用于确定可配置逻辑块和硬连线逻辑块之间的连接的块连接数据，以及用于确定部分电路之间的连接的部分电路连接数据，每个部分电路由选择的逻辑块组成 在可配置和硬连线的逻辑块之间。 这些数据由逻辑块共享，以减少集成电路中的存储器数量并提高集成电路的封装密度。

公开(公告)号：US06363010B1

公开(公告)日：2002-03-26

申请号：US09899290

申请日：2001-07-06

申请人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

发明人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

IPC分类号： G11C1604

摘要： A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When the number of multilevel data to be output to one bit line BL is 2m (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is “m”. Specifically, when the number is determined such that 22=4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.

公开(公告)号：US06198687B1

公开(公告)日：2001-03-06

申请号：US08716884

申请日：1996-09-20

申请人： Koji Sakui ,  Kazunori Ohuchi ,  Fujio Masuoka

发明人： Koji Sakui ,  Kazunori Ohuchi ,  Fujio Masuoka

IPC分类号： G11C11407

CPC分类号： G11C8/18

摘要： A semiconductor memory device which receives a row address strobe (RAS) signal and a column address strobe (CAS) signal from an external device. The device includes rewritable memory cells formed on a semiconductor substrate, a plurality of bit lines, a plurality of word lines, and a transfer gate coupled between the bit lines and input/output (I/O) lines and controlled by a column select line or signal. In one embodiment, a first transfer gate is connected between the bit lines and a second transfer gate, the second transfer gate connected between the first transfer gate and an input/output (I/O) line and controlled by a column select line (CSL). A third transfer gate may also by provided. The first transfer gate is driven in response to a clock signal which is enabled at substantially the same time as a word line of the plurality of word lines is selected during both read and write cycles. Thus, during a write cycle in which the CAS signal is enabled prior to the RAS signal, a selected CSL can be increased from a first voltage (VSS) to one of a second voltage (Vdd) and {fraction (3/2)} Vdd as soon as a column address is input.

摘要翻译： 从外部设备接收行地址选通（RAS）信号和列地址选通（CAS）信号的半导体存储器件。 该器件包括形成在半导体衬底上的可重写存储单元，多个位线，多个字线和耦合在位线和输入/输出（I / O）线之间并由列选择线控制的传输栅极 或信号。 在一个实施例中，第一传输门连接在位线和第二传输门之间，第二传输门连接在第一传输门和输入/输出（I / O）线之间，并由列选择线（CSL ）。 也可以通过提供第三传输门。 响应于在读取和写入周期期间选择多个字线的字线的基本上相同的时间使能的时钟信号来驱动第一传输门。 因此，在RAS信号之前的CAS信号被使能的写周期中，所选择的CSL可以从第一电压（VSS）增加到第二电压（Vdd）和{分数（3/2）}之一 一旦列地址被输入，就会Vdd。

公开(公告)号：US5602789A

公开(公告)日：1997-02-11

申请号：US518024

申请日：1995-08-22

申请人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

发明人： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C29/50 ,  G01R31/28

CPC分类号： G11C16/3418 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/3431 ,  G11C16/3459 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/0403 ,  G11C2211/5621

摘要： An EEPROM for storing multi-level data includes a memory cell array in which electrically erasable and programmable memory cells are arranged in matrix and each of the memory cells has at least three storage states, a write circuit for writing data to the memory cells, first and second write verify means each constituted of a sense amplifier, a data latch circuit and a detection circuit, for verifying an insufficient-written state of a memory cell and an excess-written state of a memory cell, respectively, an additional write circuit for additionally writing data to the memory cell in the insufficient-written state, and an additional erase circuit for additionally erasing data from the memory cell in the excess-written state.

摘要翻译： 用于存储多级数据的EEPROM包括存储单元阵列，其中电可擦除可编程存储器单元被排列成矩阵，并且每个存储单元具有至少三个存储状态，第一存储单元写入数据的写入电路 以及分别由读出放大器，数据锁存电路和检测电路构成的第二写入验证装置，用于分别验证存储器单元的写入不足状态和存储单元的过量写入状态，附加写入电路 在写入状态不足的情况下向存储器单元写入数据，以及附加擦除电路，用于在超量写入状态下从存储单元附加擦除数据。

公开(公告)号：US4611237A

公开(公告)日：1986-09-09

申请号：US635474

申请日：1984-07-30

申请人： Kazunori Ohuchi ,  Mitsugi Ogura ,  Kenji Natori

发明人： Kazunori Ohuchi ,  Mitsugi Ogura ,  Kenji Natori

IPC分类号： H01L29/78 ,  H01L21/82 ,  H01L23/522 ,  H01L23/535 ,  H01L29/41 ,  H01L29/417

CPC分类号： H01L23/522 ,  H01L23/535 ,  H01L29/41725 ,  H01L2924/0002

摘要： A MOS transistor integrated circuit device has at least one interconnection layer crossing the source and drain regions of a MOS transistor such that it overlies these source and drain regions. An electrical conductive layer is formed on the surface of at least one of the source and drain regions of the MOS transistor. The electrical conductive layer crosses the interconnection layer with an insulating layer therebetween such that it underlies the interconnection layer. The electrical conductive layer is separated from source and drain takeout electrodes and electrically insulated from the interconnection layer.

摘要翻译： MOS晶体管集成电路器件具有与MOS晶体管的源区和漏极区交叉的至少一个互连层，使得它覆盖在这些源极和漏极区上。 在MOS晶体管的源区和漏区中的至少一个的表面上形成导电层。 导电层在其间具有绝缘层与互连层交叉，使得其位于互连层下面。 导电层与源极和漏极引出电极分离并与互连层电绝缘。

公开(公告)号：US06545909B2

公开(公告)日：2003-04-08

申请号：US10094215

申请日：2002-03-11

申请人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

发明人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

IPC分类号： G11C1604

CPC分类号： G11C16/3459 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A memory cell array in which memory cells storable multilevel data are arranged in a matrix. Bit line controllers have latch circuits configured to latch write data and sense circuits configured to sense read data. Bit lines connect the bit line controllers and the memory cells. The bit lines supply write data from the latch circuits to the memory cells during data write mode and supply read data from the memory cells to the sense circuits during data read mode. The number of the multilevel data is 4 and the number of the sense circuits is 2, or the number of the multilevel data is 8 and the number of the sense circuits is 3.

摘要翻译： 存储单元阵列，其中存储单元可存储多级数据以矩阵形式排列。 位线控制器具有被配置为锁存写入数据和被配置为感测读取数据的感测电路的锁存电路。 位线连接位线控制器和存储单元。 在数据写入模式期间，位线将写入数据从锁存电路提供给存储器单元，并且在数据读取模式期间将读取数据从存储器单元提供给读出电路。 多级数据的数量为4，感测电路的数量为2，多级数据的数量为8，感测电路的数量为3。

公开(公告)号：US6044013A

公开(公告)日：2000-03-28

申请号：US314446

申请日：1999-05-19

申请人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

发明人： Tomoharu Tanaka ,  Kazunori Ohuchi ,  Toru Tanzawa ,  Ken Takeuchi

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

CPC分类号： G11C16/3459 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3454 ,  G11C7/1006 ,  G11C7/1078 ,  G11C7/12 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A bit line controller is provided for connecting a data input/output line and one bit line BL to each other. The bit line controller has a data latch for latching multilevel write data supplied from the data input/output line to the memory cell and a sense amplifier for sensing and latching data output to one bit line BL from the memory cell transistor. When the number of multilevel data to be output to one bit line BL is 2.sup.m (m is a natural number not smaller than 2)=n-level, the number of each of the data latch and sense amplifier is "m". Specifically, when the number is determined such that 2.sup.2 =4, the number of each of the data latch and the sense amplifier is two. As a result, there is provided a nonvolatile semiconductor memory device capable of decreasing the size of a column-system circuit and realizing a highly integrated structure.

摘要翻译： 提供了用于将数据输入/输出线和一个位线BL彼此连接的位线控制器。 位线控制器具有用于将从数据输入/输出线提供的多电平写入数据锁存到存储单元的数据锁存器和用于感测和锁存从存储单元晶体管输出到一个位线BL的数据的读出放大器。 当要输出到一个位线BL的多电平数据的数量为2m（m是不小于2的自然数）= n电平时，每个数据锁存器和读出放大器的数量为“m”。 具体地说，当确定数字使得22 = 4时，每个数据锁存器和读出放大器的数量是两个。 结果，提供了一种能够减小列系统电路的尺寸并实现高度集成的结构的非易失性半导体存储器件。

公开(公告)号：US5933436A

公开(公告)日：1999-08-03

申请号：US611818

申请日：1996-03-06

申请人： Toru Tanzawa ,  Tomoharu Tanaka ,  Riichiro Shirota ,  Kazunori Ohuchi

发明人： Toru Tanzawa ,  Tomoharu Tanaka ,  Riichiro Shirota ,  Kazunori Ohuchi

IPC分类号： G06F12/16 ,  G06F11/10 ,  H03M13/15 ,  G11C29/00

CPC分类号： G06F11/1008 ,  H03M13/151

摘要： An error correction/detection circuit including a syndrome generating circuit for generating a syndrome from information data and check data input in a first cycle; and an error position/size calculating circuit for calculating a position and a size of an error from said syndrome; and an error correction circuit for correcting an error for at least information data input in a second cycle on a basis of the position and the size of the error obtained in said error position/size calculating circuit and for outputting at least error-corrected information data.

摘要翻译： 一种纠错/检测电路，包括：从第一周期输入的信息数据和检查数据产生校正子的校正子产生电路; 以及误差位置/尺寸计算电路，用于计算所述综合征的误差的位置和尺寸; 以及误差校正电路，用于根据在所述误差位置/尺寸计算电路中获得的误差的位置和尺寸，校正至少在第二周期中输入的信息数据的误差，并且至少输出错误校正的信息数据 。