公开(公告)号：US06327654B1

公开(公告)日：2001-12-04

申请号：US09151774

申请日：1998-09-11

申请人： Yukihito Oowaki ,  Hiroshige Fujii ,  Hideo Shimizu ,  Takehisa Kato ,  Naoki Endo ,  Atsushi Masuda ,  Hiroaki Nishi ,  Kazunori Ohuchi ,  Masatoshi Sekine

发明人： Yukihito Oowaki ,  Hiroshige Fujii ,  Hideo Shimizu ,  Takehisa Kato ,  Naoki Endo ,  Atsushi Masuda ,  Hiroaki Nishi ,  Kazunori Ohuchi ,  Masatoshi Sekine

IPC分类号： G06F1130

CPC分类号： G06F21/72 ,  H04L9/0625 ,  H04L2209/08 ,  H04L2209/122 ,  H04L2209/125

摘要： A semiconductor integrated circuit for cryptographic process according to the present invention, comprises a randomizing unit for randomizing first input data which is one of two divided parts of input data based on configuration information to identify an algorithm in randomizing process, a function F portion for receiving data which have been subjected to the randomizing process and then applying coding process to the data, and an exclusive logical sum circuit for receiving second input data which is other of two divided parts of the input data and output data from the function F portion and then outputting an exclusive logical sum of the second input data and the output data.

摘要翻译： 根据本发明的用于密码处理的半导体集成电路包括：随机化单元，用于基于配置信息随机化作为输入数据的两个分割部分之一的第一输入数据，以识别随机化过程中的算法;函数F部分，用于接收 已经经过随机化处理然后对数据进行编码处理的数据，以及用于接收作为输入数据的两个分割部分中的另外两个部分的第二输入数据和来自功能F部分的输出数据的异或逻辑和电路， 输出第二输入数据和输出数据的异或逻辑和。

公开(公告)号：US6157997A

公开(公告)日：2000-12-05

申请号：US38834

申请日：1998-03-12

申请人： Yukihito Oowaki ,  Hiroshige Fujii ,  Masatoshi Sekine

发明人： Yukihito Oowaki ,  Hiroshige Fujii ,  Masatoshi Sekine

IPC分类号： G06F7/00 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/78

CPC分类号： G06F9/3822 ,  G06F15/7867 ,  G06F9/30181 ,  G06F9/30196 ,  G06F9/3897

摘要： Part or all of an instruction decoder is constructed of a first reconfigurable circuit wherein a circuit structure thereof can be changed according to an external signal. Further, a second reconfigurable circuit which is connected to output side of a register file as part of processing unit and wherein a circuit structure thereof can be changed according to an external signal is preliminarily provided. For special use, to achieve a predetermined operating function, the second reconfigurable circuit is reconstructed by the external signal. Further, a particular instruction corresponding to the predetermined operating function is set, and the first reconfigurable circuit is so reconstructed by an external signal that when the particular instruction is inputted, a corresponding control signal is outputted. When the particular instruction is executed, the first reconfigurable circuit outputs a control signal and the second reconfigurable circuit executes the predetermined operating function by that control signal.

摘要翻译： 指令解码器的一部分或全部由第一可重构电路构成，其中其电路结构可以根据外部信号而改变。 此外，预先提供连接到作为处理单元的一部分的寄存器堆的输出侧并且其中其电路结构可以根据外部信号改变的第二可重新配置电路。 为了特别使用，为了实现预定的操作功能，第二可重构电路由外部信号重建。 此外，设置与预定操作功能相对应的特定指令，并且通过外部信号重构第一可重新配置电路，当输入特定指令时，输出相应的控制信号。 当执行特定指令时，第一可重新配置电路输出控制信号，第二可重新配置电路通过该控制信号执行预定的操作功能。

公开(公告)号：US06349395B2

公开(公告)日：2002-02-19

申请号：US09154027

申请日：1998-09-16

申请人： Kazunori Ohuchi ,  Masako Yoshida ,  Yukihito Oowaki ,  Hiroshige Fujii ,  Masatoshi Sekine

发明人： Kazunori Ohuchi ,  Masako Yoshida ,  Yukihito Oowaki ,  Hiroshige Fujii ,  Masatoshi Sekine

IPC分类号： G01R3128

CPC分类号： G01R31/318516

摘要： An integrated circuit has configurable logic blocks that are reconfigurable, hard-wired logic blocks that carry out fixed operations, and a memory. The memory stores configuration data for configuring the configurable logic blocks, block-connection data for determining connections between the configurable and hard-wired logic blocks, and partial-circuit-connection data for determining connections between partial circuits each of which consists of logic blocks selected among the configurable and hard-wired logic blocks. These pieces of data are shared by the logic blocks to reduce the number of memories in the integrated circuit and improve the packaging density of the integrated circuit.

摘要翻译： 集成电路具有可配置逻辑块，其是可重新配置的，执行固定操作的硬连线逻辑块，以及存储器。 存储器存储用于配置可配置逻辑块的配置数据，用于确定可配置逻辑块和硬连线逻辑块之间的连接的块连接数据，以及用于确定部分电路之间的连接的部分电路连接数据，每个部分电路由选择的逻辑块组成 在可配置和硬连线的逻辑块之间。 这些数据由逻辑块共享，以减少集成电路中的存储器数量并提高集成电路的封装密度。

公开(公告)号：US6112163A

公开(公告)日：2000-08-29

申请号：US38373

申请日：1998-03-11

申请人： Yukihito Oowaki ,  Masatoshi Sekine ,  Hiroshige Fujii

发明人： Yukihito Oowaki ,  Masatoshi Sekine ,  Hiroshige Fujii

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G06F11/22 ,  G01R15/12

CPC分类号： G01R31/318566

摘要： A reconfigurable circuit is reconstructed to three or more operating circuit blocks. Upon testing, the same data is inputted to each of the reconstructed operating circuit blocks. A majority circuit formed in the reconfigurable circuit compares results of operations of the operating circuit blocks and outputs information indicating which of the operating circuit blocks is in trouble.

摘要翻译： 可重构电路被重建为三个或更多个操作电路块。 在测试时，将相同的数据输入到每个重建的操作电路块。 形成在可重构电路中的多数电路比较了操作电路块的操作结果并输出指示哪些操作电路块处于故障状态的信息。

公开(公告)号：US6026480A

公开(公告)日：2000-02-15

申请号：US37067

申请日：1998-03-09

申请人： Yukihito Oowaki ,  Hiroshige Fujii ,  Masatoshi Sekine

发明人： Yukihito Oowaki ,  Hiroshige Fujii ,  Masatoshi Sekine

IPC分类号： G06F11/28 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F11/00 ,  G06F11/20 ,  G06F11/22 ,  G06F15/78 ,  G06F9/28

CPC分类号： G06F9/328 ,  G06F11/004 ,  G06F11/20 ,  G06F9/30181 ,  G06F9/30196 ,  G06F9/3861

摘要： A reconfigurable circuit wherein part or all of an instruction or a result of decoding thereof and output of said register file are inputted and a circuit structure thereof can be changed by an external signal is provided. If a bug occurs when part or all of the instruction or the result of decoding thereof and the output of the register file satisfy a particular condition, the reconfigurable circuit is reconstructed by an external signal so as to output a first signal under that particular condition. An interrupt control circuit controls a processing unit so as to carry out processing based on the first signal or processing to avoid the bug when the first signal is inputted.

摘要翻译： 一种可重新配置电路，其中提供其指令或其解码结果和所述寄存器文件的输出的部分或全部，并且其电路结构可以通过外部信号改变。 如果当部分或全部指令或其解码结果和寄存器文件的输出满足特定条件时发生错误，则可通过外部信号重建可重构电路，以便在该特定条件下输出第一信号。 中断控制电路控制处理单元，以便基于第一信号或处理进行处理，以便在输入第一信号时避免错误。

公开(公告)号：US07685552B2

公开(公告)日：2010-03-23

申请号：US11690985

申请日：2007-03-26

申请人： Fujio Ishihara ,  Ryubi Okuda ,  Toshihiko Himeno ,  Hiroshige Fujii

发明人： Fujio Ishihara ,  Ryubi Okuda ,  Toshihiko Himeno ,  Hiroshige Fujii

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/62 ,  G06F2217/84

摘要： This invention concerns a semiconductor integrated circuit device comprising a plurality of circuit elements arranged in a chip and operating in response to a same clock signal; clock buffers arranged at intersecting points decided based on positions of the plurality of circuit elements, the intersecting points being included in intersecting points of a pseudo mesh virtually assumed to cover up a region in the chip including the plurality of circuit elements; and a main wiring transmitting the clock signal to the clock buffers.

摘要翻译： 本发明涉及一种半导体集成电路器件，其包括布置在芯片中并响应于相同时钟信号而工作的多个电路元件; 布置在基于多个电路元件的位置确定的相交点处的时钟缓冲器，所述交点包括在虚拟网格的相交点中，虚拟地假定为覆盖包括多个电路元件的芯片中的区域; 以及将时钟信号发送到时钟缓冲器的主线。

公开(公告)号：US06617902B2

公开(公告)日：2003-09-09

申请号：US10101694

申请日：2002-03-21

申请人： Motoki Tokumasu ,  Hiroshige Fujii

发明人： Motoki Tokumasu ,  Hiroshige Fujii

IPC分类号： H03K3356

CPC分类号： H03K3/356121 ,  H03K3/012

摘要： A semiconductor holding device comprises a first transistor circuit including a P type first transistor connected to a first power source, an N type second transistor connected to the first transistor and an N type third transistor connected to the second transistor and a second power source, and a second transistor circuit including a P type fourth transistor connected to the first power source, an N type fifth transistor connected to the fourth transistor and an N type sixth transistor connected between the fifth transistor and the second power source, an input signal being supplied to gates of the P type first transistor and the N type second transistor, a clock signal being supplied to gates of the N type third and sixth transistors, a node of the first and second transistors being connected to gates of the fourth and fifth transistors, and a node of the fourth and fifth transistors serving as an output node.

公开(公告)号：US06393521B1

公开(公告)日：2002-05-21

申请号：US09140280

申请日：1998-08-26

申请人： Hiroshige Fujii

发明人： Hiroshige Fujii

IPC分类号： G06F1200

CPC分类号： G06F12/0848

摘要： An information processing apparatus comprises a first memory, a first cache memory provided for the first memory and having a cache line size according to the bandwidth of the first memory, a second memory having a bandwidth different from that of the first memory, and a second cache memory provided for the second memory and having a cache line size according to the bandwidth of the second memory.

摘要翻译： 信息处理装置包括：第一存储器，为第一存储器提供的第一高速缓冲存储器，具有根据第一存储器的带宽的高速缓存行大小;第二存储器，具有与第一存储器的带宽不同的带宽;第二存储器， 为第二存储器提供的缓存存储器，并且具有根据第二存储器的带宽的高速缓存行大小。

公开(公告)号：US20070240087A1

公开(公告)日：2007-10-11

申请号：US11690985

申请日：2007-03-26

申请人： Fujio ISHIHARA ,  Ryubi Okuda ,  Toshihiko Himeno ,  Hiroshige Fujii

发明人： Fujio ISHIHARA ,  Ryubi Okuda ,  Toshihiko Himeno ,  Hiroshige Fujii

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5045 ,  G06F2217/62 ,  G06F2217/84

摘要： This invention concerns a semiconductor integrated circuit device comprising a plurality of circuit elements arranged in a chip and operating in response to a same clock signal; clock buffers arranged at intersecting points decided based on positions of the plurality of circuit elements, the intersecting points being included in intersecting points of a pseudo mesh virtually assumed to cover up a region in the chip including the plurality of circuit elements; and a main wiring transmitting the clock signal to the clock buffers.

摘要翻译： 本发明涉及一种半导体集成电路器件，其包括布置在芯片中并响应于相同时钟信号而工作的多个电路元件; 布置在基于多个电路元件的位置确定的相交点处的时钟缓冲器，所述交点包括在虚拟网格的相交点中，虚拟地假定为覆盖包括多个电路元件的芯片中的区域; 以及将时钟信号发送到时钟缓冲器的主线。