公开(公告)号：US06643191B2

公开(公告)日：2003-11-04

申请号：US10102308

申请日：2002-03-19

申请人： Yun-sang Lee ,  Jong-hyun Choi ,  Sang-seok Kang

发明人： Yun-sang Lee ,  Jong-hyun Choi ,  Sang-seok Kang

IPC分类号： G11C700

CPC分类号： G11C29/44 ,  G11C8/12

摘要： A semiconductor memory device and a method of generating a chip selection signal that enable the analysis of the causes of defects of defective memory devices selected by a user from a system with a plurality of memory devices and the fixing the defects are provided. The semiconductor memory device includes a programming register, an input buffer control circuit, and a chip selection circuit. The programming register activates an output signal in response to an address and a command input from the outside. The input buffer control circuit activates the plurality of data input buffer circuits in response to the output signal of the programming register. The chip selection circuit activates a defect detecting & repairing circuit, such as a repair circuit or a test time shortening circuit, when at least one of output signals of the plurality of data input buffer circuits is in a first logic state.

公开(公告)号：US06982917B2

公开(公告)日：2006-01-03

申请号：US10192406

申请日：2002-07-10

申请人： Yun-sang Lee ,  Won-chang Jung

发明人： Yun-sang Lee ,  Won-chang Jung

IPC分类号： G11C7/00

CPC分类号： G11C11/406

摘要： Circuits and methods for refreshing memory banks in a DRAM are provided. A refresh circuit is provided in a DRAM having at least one memory bank and a plurality of word lines connected to memory locations in the memory bank. The word lines are subdivided into first and second groups of subword lines. The refresh circuit includes a delay circuit, a first driving circuit, and a second driving circuit. The delay circuit receives a refresh signal and outputs a delayed refresh signal a predetermined time delay later. The first driving circuit responds to the refresh signal by driving word lines in the first group of subword lines and the second driving circuit responds to the delayed refresh signal by driving word lines in the second group of subword lines.

摘要翻译： 提供了用于刷新DRAM中的存储体的电路和方法。 在具有至少一个存储体和连接到存储体中的存储器位置的多条字线的DRAM中提供刷新电路。 字线被细分为第一和第二组子字线。 刷新电路包括延迟电路，第一驱动电路和第二驱动电路。 延迟电路接收刷新信号并且稍后在预定的时间延迟中输出延迟的刷新信号。 第一驱动电路通过驱动第一组子字线中的字线来响应刷新信号，并且第二驱动电路通过驱动第二组子字线中的字线来响应延迟的刷新信号。

公开(公告)号：US07734967B2

公开(公告)日：2010-06-08

申请号：US11863500

申请日：2007-09-28

申请人： Hoe-ju Chung ,  Yun-sang Lee

发明人： Hoe-ju Chung ,  Yun-sang Lee

IPC分类号： G11C29/00

CPC分类号： G11C29/14 ,  G11C29/12015 ,  G11C2029/3602

摘要： A semiconductor memory device, having a test mode and a normal mode, includes a frequency multiplier and a test command sequence generator. The frequency multiplier receives a test clock signal in the test mode and generates multiple internal test clock signals, each of which has a frequency equal to a frequency of an operation clock signal in the normal mode. The test clock signal has a frequency lower than the frequency of the operation clock signal. The test command sequence generator generates at least one command signal in response to the internal test clock signals in the test mode. The at least one command signal corresponds to at least one operation timing parameter of the semiconductor memory device that is to be measured. The frequency multiplier may include a Phase Locked Loop (PLL) or a Delay Locked Loop (DLL).

摘要翻译： 具有测试模式和正常模式的半导体存储器件包括倍频器和测试命令序列发生器。 倍频器在测试模式下接收测试时钟信号，并产生多个内部测试时钟信号，每个内部测试时钟信号的频率等于正常模式下的工作时钟信号的频率。 测试时钟信号的频率低于操作时钟信号的频率。 测试命令序列发生器响应于测试模式中的内部测试时钟信号而产生至少一个命令信号。 所述至少一个命令信号对应于待测量的半导体存储器件的至少一个操作定时参数。 倍频器可以包括锁相环（PLL）或延迟锁定环（DLL）。

公开(公告)号：US07054202B2

公开(公告)日：2006-05-30

申请号：US10792425

申请日：2004-03-03

申请人： Yun-sang Lee ,  Jung-bae Lee ,  One-gyun La ,  Sung-ryul Kim

发明人： Yun-sang Lee ,  Jung-bae Lee ,  One-gyun La ,  Sung-ryul Kim

IPC分类号： G11C16/04

CPC分类号： G11C7/1078 ,  G11C7/1027 ,  G11C2207/107

摘要： Integrated circuit memory devices include a memory cell array that is configured to write N data bits in parallel and a write data path that is configured to serially receive 2N data bits from an external terminal. The write data path includes 2N write data buffers that are configured to store the 2N data bits, 2N switches, and N data lines that are configured to connect at least N of the 2N switches to the memory cell array to write therein N data bits in parallel. A reduced number of local data lines and/or global data lines may be provided.

摘要翻译： 集成电路存储器件包括被配置为并行地写入N个数据位的存储器单元阵列和被配置为从外部端子串行地接收2N个数据位的写入数据路径。 写数据路径包括2N个写入数据缓冲器，其被配置为存储2N个数据位，2N个开关和N个数据线，其被配置为将2N个开关中的至少N个连接到存储单元阵列以在其中写入N个数据位 平行。 可以提供减少数量的本地数据线和/或全局数据线。

公开(公告)号：US6069812A

公开(公告)日：2000-05-30

申请号：US136831

申请日：1998-08-20

申请人： Yun-sang Lee ,  Jun-young Jeon

发明人： Yun-sang Lee ,  Jun-young Jeon

IPC分类号： G11C11/401 ,  G11C5/02 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C5/025

摘要： Integrated circuit memory devices include a rectangular integrated circuit memory device substrate that includes a pair of short sides, a pair of long sides and a pair of opposing faces. The substrate also includes an array of memory cells and peripheral circuits therein. A plurality of spaced apart rows of input/output pads on one of the faces extend parallel to the short sides. The face is free of (i.e. does not include) a row of input/output pads that extends parallel to the long sides. The input/output pads are preferably arranged on the integrated circuit memory device substrate, relative to the circuits in the integrated circuit memory device substrate. More specifically, the integrated circuit memory device includes a plurality of memory cell array blocks, first decoder blocks and second decoder blocks in the substrate. A respective first decoder block extends parallel to the short sides adjacent a respective memory cell array block and opposite a short side. A respective second decoder block extends parallel to the long sides, between adjacent memory cell array blocks. The plurality of input/output pads are included between the short sides and the memory cell array blocks adjacent thereto and between the first decoder blocks.

摘要翻译： 集成电路存储器件包括矩形集成电路存储器件衬底，其包括一对短边，一对长边和一对相对面。 衬底还包括其中的存储器单元阵列和外围电路。 在其中一个面上的多个间隔开的输入/输出焊盘行平行于短边延伸。 脸部没有（即不包括）一排平行于长边延伸的输入/输出垫片。 相对于集成电路存储器件衬底中的电路，输入/输出焊盘优选地布置在集成电路存储器件衬底上。 更具体地，集成电路存储器件包括衬底中的多个存储单元阵列块，第一解码器块和第二解码器块。 相应的第一解码器块平行于相邻的存储单元阵列块的短边延伸并且与短边相对。 相应的第二解码器块在相邻的存储单元阵列块之间平行于长边延伸。 多个输入/输出焊盘包括在短边和与其相邻的存储单元阵列块之间和第一解码器块之间。

公开(公告)号：US07652942B2

公开(公告)日：2010-01-26

申请号：US11757099

申请日：2007-06-01

申请人： Myeong-o Kim ,  Yun-sang Lee

发明人： Myeong-o Kim ,  Yun-sang Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/14 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2207/005

摘要： A sense amplifier includes a reference signal providing unit and an internal sense amplification unit. The reference signal providing unit provides a reference bit line signal in response to a reference control signal. The internal sense amplification unit receives the reference bit line signal and data signals that correspond to the data. The received signals are provided through bit lines connected to the memory cell array. The internal sense amplification unit senses the received reference bit line signal and the data signals and amplifies the sensed signals. The sense amplifier senses data stored in memory cells connected to dummy bit lines of the outmost memory cell array of a semiconductor memory device such that the memory cells that are not used can be used. Accordingly, the design area and cost of the semiconductor memory device can be reduced.

摘要翻译： 读出放大器包括参考信号提供单元和内部检测放大单元。 参考信号提供单元响应于参考控制信号提供参考位线信号。 内部检测放大单元接收对应于数据的参考位线信号和数据信号。 接收的信号通过连接到存储单元阵列的位线来提供。 内部感测放大单元感测接收的参考位线信号和数据信号并放大所感测的信号。 感测放大器感测存储在连接到半导体存储器件的最外存储单元阵列的虚拟位线的存储器单元中的数据，使得可以使用未使用的存储器单元。 因此，可以减少半导体存储器件的设计面积和成本。

公开(公告)号：US20080056039A1

公开(公告)日：2008-03-06

申请号：US11757099

申请日：2007-06-01

申请人： Myeong-o Kim ,  Yun-sang Lee

发明人： Myeong-o Kim ,  Yun-sang Lee

IPC分类号： G11C7/06

CPC分类号： G11C7/14 ,  G11C7/06 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2207/005

摘要： A sense amplifier includes a reference signal providing unit and an internal sense amplification unit. The reference signal providing unit provides a reference bit line signal in response to a reference control signal. The internal sense amplification unit receives the reference bit line signal and data signals that correspond to the data. The received signals are provided through bit lines connected to the memory cell array. The internal sense amplification unit senses the received reference bit line signal and the data signals and amplifies the sensed signals. The sense amplifier senses data stored in memory cells connected to dummy bit lines of the outmost memory cell array of a semiconductor memory device such that the memory cells that are not used can be used. Accordingly, the design area and cost of the semiconductor memory device can be reduced.

摘要翻译： 读出放大器包括参考信号提供单元和内部检测放大单元。 参考信号提供单元响应于参考控制信号提供参考位线信号。 内部检测放大单元接收对应于数据的参考位线信号和数据信号。 接收的信号通过连接到存储单元阵列的位线来提供。 内部感测放大单元感测接收的参考位线信号和数据信号并放大所感测的信号。 感测放大器感测存储在连接到半导体存储器件的最外存储单元阵列的虚拟位线的存储器单元中的数据，使得可以使用未使用的存储器单元。 因此，可以减少半导体存储器件的设计面积和成本。

公开(公告)号：US06804163B2

公开(公告)日：2004-10-12

申请号：US10305986

申请日：2002-11-29

申请人： Yun-sang Lee ,  Jung-bae Lee

发明人： Yun-sang Lee ,  Jung-bae Lee

IPC分类号： G11C800

CPC分类号： G11C7/12 ,  G11C5/025 ,  G11C7/06 ,  G11C7/10

摘要： A semiconductor memory device that minimizes chip area is provided. The semiconductor memory device includes local input/output (I/O) lines, global I/O lines, and a memory core that is coupled between a bit line and a complementary bit line. The memory core includes a memory cell array, a bit line equalizer circuit, a PMOS sense amplifier (S/A), a PMOS S/A driving circuit for driving the PMOS S/A, a transmission gate circuit, an NMOS S/A, and an NMOS S/A driving circuit for driving the NMOS S/A. First and second transistors for connecting the local I/O lines to the global I/O lines are installed between adjacent bit lines. The PMOS S/A driving circuit, which is a first driving transistor, and the NMOS S/A driving circuit, which is a second driving transistor, are also installed between adjacent bit lines. Because the semiconductor memory device arranges a PMOS S/A driving circuit, an NMOS S/A driving circuit, and a gating circuit for connecting local I/O lines to global I/O lines, between adjacent bit lines, the chip area is reduced.

摘要翻译： 提供了最小化芯片面积的半导体存储器件。 半导体存储器件包括本地输入/输出（I / O）线，全局I / O线和耦合在位线和互补位线之间的存储器核。 存储器芯包括存储单元阵列，位线均衡器电路，PMOS读出放大器（S / A），用于驱动PMOS S / A的PMOS S / A驱动电路，传输门电路，NMOS S / A 以及用于驱动NMOS S / A的NMOS S / A驱动电路。 用于将本地I / O线连接到全局I / O线的第一和第二晶体管安装在相邻位线之间。 作为第一驱动晶体管的PMOS S / A驱动电路和作为第二驱动晶体管的NMOS S / A驱动电路也安装在相邻位线之间。 由于半导体存储器件在相邻位线之间配置PMOS S / A驱动电路，NMOS S / A驱动电路和用于将本地I / O线连接到全局I / O线的选通电路，芯片面积减小 。

公开(公告)号：US07808858B2

公开(公告)日：2010-10-05

申请号：US11875171

申请日：2007-10-19

申请人： Yun-sang Lee ,  Jung-bae Lee

发明人： Yun-sang Lee ,  Jung-bae Lee

IPC分类号： G11C8/00

CPC分类号： G11C8/08

摘要： A method and circuit are provided for driving a word line. The word line driving circuit includes first and second power drivers, a switching unit and a word line driver. The first power driver is driven to a boosting voltage level and the second power driver is driven to an internal power voltage level. The switching unit transfers a first output of the first power driver to the word line driver in response to a first switching signal and transfers a second output of the second power driver to the word line driver in response to a second switching signal. The word line driver alternately drives a word line to the first output and the second output transferred from the switching unit in response to a word line driving signal.

摘要翻译： 提供了用于驱动字线的方法和电路。 字线驱动电路包括第一和第二电源驱动器，开关单元和字线驱动器。 第一个功率驱动器被驱动到升压电压电平，第二个功率驱动器被驱动到内部电源电压电平。 切换单元响应于第一切换信号将第一功率驱动器的第一输出传送到字线驱动器，并响应于第二切换信号将第二功率驱动器的第二输出传送到字线驱动器。 字线驱动器响应于字线驱动信号交替地驱动字线到第一输出和从开关单元传送的第二输出。

公开(公告)号：US07313046B2

公开(公告)日：2007-12-25

申请号：US11214657

申请日：2005-08-30

申请人： Sung-ho Choi ,  Yun-sang Lee

发明人： Sung-ho Choi ,  Yun-sang Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40618

摘要： A semiconductor memory device includes a plurality of memory banks. A refresh control block is responsive to a control address that identifies at least one of the plurality of memory banks to be refreshed. The refresh control block is configured to control refreshing of the at least one of the plurality of memory banks to be refreshed. The control address is used during read and/or write operations of the plurality of memory banks.

摘要翻译： 半导体存储器件包括多个存储体。 刷新控制块响应于识别要刷新的多个存储器组中的至少一个的控制地址。 刷新控制块被配置为控制要刷新的多个存储体中的至少一个的刷新。 在多个存储体的读取和/或写入操作期间使用控制地址。