公开(公告)号：US06569699B1

公开(公告)日：2003-05-27

申请号：US09495347

申请日：2000-02-01

申请人： Yung-Tao Lin ,  Sik On Kong

发明人： Yung-Tao Lin ,  Sik On Kong

IPC分类号： H01L2100

CPC分类号： G02F1/136277 ,  G02F1/133553 ,  G02F2001/133357

摘要： A method of fabricating an LCD-on-silicon pixel device including the following steps. A substrate having an upper layer of silicon is provided. A via is formed in the silicon layer. An opaque conducting layer is deposited over the silicon layer, filling the via. The opaque conducting layer is planarized a reflective layer is deposited over the opaque conducting layer. Alternatively, the via may be formed by a deposition and etch back process with one metal. An opaque conducting layer is then deposited and planarized before deposition of the reflective layer. An LCD-on-silicon pixel device, comprises a substrate having an upper silicon layer. The upper silicon layer has a plug therein comprised of an opaque conducting material. Over the upper silicon layer and the opaque conducting plug is a planar opaque conducting layer and a planar reflective layer is over the planar opaque conducting layer.

摘要翻译： 一种制造包括以下步骤的硅上硅像素装置的方法。 提供了具有上层硅的衬底。 在硅层中形成通孔。 在硅层上沉积不透明导电层，填充通孔。 不透明导电层被平坦化，反射层沉积在不透明导电层上。 或者，可以通过用一种金属的沉积和回蚀工艺形成通孔。 然后在沉积反射层之前沉积不平坦的导电层并进行平坦化。 一种硅上像素元件，包括具有上硅层的衬底。 上硅层具有由不透明导电材料构成的塞子。 在上硅层和不透明导电插塞之上是平面不透明导电层，并且平面反射层在平面不透明导电层之上。

公开(公告)号：US06180430B2

公开(公告)日：2001-01-30

申请号：US09458726

申请日：1999-12-13

申请人： Sik On Kong ,  Dai Feng ,  Yung-Tao Lin ,  Robert Chin Fu Tsai

发明人： Sik On Kong ,  Dai Feng ,  Yung-Tao Lin ,  Robert Chin Fu Tsai

IPC分类号： H01L2100

CPC分类号： G02F1/133512 ,  G02F1/136

摘要： A method of fabricating an LCD-on-silicon device, comprising the following steps. A semiconductor structure having a control transistor formed therein is provided. The control transistor having a source and a drain. An interlevel dielectric (ILD) layer over the semiconductor structure is provided. Source/drain (S/D) plugs contacting the source and drain through contact openings in said ILD layer are provided. M1 lines are formed over the ILD layer and connected to at least the S/D plugs. An M1 intermetal dielectric (IMD) layer is deposited and patterned over the M1 lines to form M1 contact openings exposing at least some of the M1 metal lines. M1 metal plugs are formed within the M1 contact openings and M2 metal islands connected to, and integral with, at least the M1 metal plugs. The M2 metal islands having exposed side walls. Sidewall spacers are formed on the exposed M2 metal islands side walls. A second M2 metallization layer is deposited and patterned over the M2 metal islands to form a shielding layer adjacent to and contiguous with the sidewall spacers. The M2 metal islands, sidewall spacers, and shielding layer form a light shielding layer. At least one additional dielectric and conductive layer is formed over the light shielding layer and the M1 intermetal dielectric (IMD) layer. LCD pixels are then formed thereover.

摘要翻译： 一种制造硅 - 硅器件的方法，包括以下步骤。 提供了其中形成有控制晶体管的半导体结构。 控制晶体管具有源极和漏极。 提供半导体结构上的层间电介质（ILD）层。 提供了通过所述ILD层中的接触开口接触源极和漏极的源极/漏极（S / D）插塞。 M1线形成在ILD层上并且连接到至少S / D插头。 在M1线上沉积并图案化M1金属间电介质（IMD）层，以形成暴露至少一些M1金属线的M1接触开口。 M1金属插塞形成在M1接触开口和M2金属岛之间，M2金属岛连接到至少M1金属插头并与其成一体。 M2金属岛具有暴露的侧壁。 在暴露的M2金属岛侧壁上形成侧壁间隔物。 在M2金属岛上沉积和图案化第二M2金属化层以形成与侧壁间隔物相邻并邻接的屏蔽层。 M2金属岛，侧壁间隔物和屏蔽层形成遮光层。 在遮光层和M1金属间电介质（IMD）层上形成至少一个附加的电介质层和导电层。 然后在其上形成LCD像素。

公开(公告)号：US06822268B2

公开(公告)日：2004-11-23

申请号：US10437332

申请日：2003-05-13

申请人： Yung-Tao Lin ,  Sik On Kong

发明人： Yung-Tao Lin ,  Sik On Kong

IPC分类号： H01L3300

CPC分类号： G02F1/136277 ,  G02F1/133553 ,  G02F2001/133357

摘要： A method of fabricating an LCD-on-silicon pixel device, comprising the following steps. A substrate having an upper layer of silicon is provided. A via is formed in the silicon layer. An opaque conducting layer is deposited over the silicon layer, filling the via. The opaque conducting layer is planarized a reflective layer is deposited over the opaque conducting layer. Alternatively, the via may be formed by a deposition and etch back process with one metal. An opaque conducting layer is then deposited and planarized before deposition of the reflective layer. An LCD-on-silicon pixel device, comprises a substrate having an upper silicon layer. The upper silicon layer has a plug therein comprised of an opaque conducting material. Over the upper silicon layer and the opaque conducting plug is a planar opaque conducting layer and a planar reflective layer is over the planar opaque conducting layer.

摘要翻译： 一种制造硅上像素像素装置的方法，包括以下步骤。 提供了具有上层硅的衬底。 在硅层中形成通孔。 在硅层上沉积不透明导电层，填充通孔。 不透明导电层被平坦化，反射层沉积在不透明导电层上。 或者，可以通过用一种金属的沉积和回蚀工艺形成通孔。 然后在沉积反射层之前沉积不平坦的导电层并进行平坦化。 一种硅上像素元件，包括具有上硅层的衬底。 上硅层具有由不透明导电材料构成的塞子。 在上硅层和不透明导电插塞之上是平面不透明导电层，并且平面反射层在平面不透明导电层之上。

公开(公告)号：US06569762B2

公开(公告)日：2003-05-27

申请号：US10167862

申请日：2002-06-11

申请人： Sik On Kong

发明人： Sik On Kong

IPC分类号： H01L2302

CPC分类号： H01L25/0657 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01019 ,  H01L2924/3011

摘要： In the present invention a high performance package is described where semiconductor chips are stacked together in a pancake like fashion with inter chip communications facilitated by chip to chip vias formed through the material of each chip. The chip to chip vias are created by etching and filling a hole from the back of a chip through the silicon substrate stopping at the first level of metalization and invoking the wiring of the chip to complete the path to the top side. The chip in the stack are aligned so that chip to chip vias form columns. Signal and power can travel the full length of a column from the bottom chip to the chip on top, or the wiring within the chips can interrupt the signal flow and form interstitial connections. Interstitial connections can also be used to enhance the wireability between chips in the stack. To accommodate cooling the chips in the stack are made in varying sizes and are ordered in size from the largest at the bottom of the stack to the smallest at the top of the stack. This provides a stair case like structure to allow heat sinks to be attached to each step formed by a chip and the smaller chip above. An interface substrate sits at the bottom of the stack and provides for communication external to the stack by connecting the columns of chip to chip vias to an array of pins to mate with a connector. The short distances that signals must travel lends this three dimensional stacked chip package to high performance for off chip communications.

公开(公告)号：US06444576B1

公开(公告)日：2002-09-03

申请号：US09595060

申请日：2000-06-16

申请人： Sik On Kong

发明人： Sik On Kong

IPC分类号： H01L2302

CPC分类号： H01L25/0657 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01019 ,  H01L2924/3011

摘要： In the present invention a high performance package is described where semiconductor chips are stacked together in a pancake like fashion with inter chip communications facilitated by chip to chip vias formed through the material of each chip. The chip to chip vias are created by etching and filling a hole from the back of a chip through the silicon substrate stopping at the first level of metalization and invoking the wiring of the chip to complete the path to the top side. The chip in the stack are aligned so that chip to chip vias form columns. Signal and power can travel the full length of a column from the bottom chip to the chip on top, or the wiring within the chips can interrupt the signal flow and form interstitial connections. Interstitial connections can also be used to enhance the wireability between chips in the stack. To accommodate cooling the chips in the stack are made in varying sizes and are ordered in size from the largest at the bottom of the stack to the smallest at the top of the stack. This provides a stair case like structure to allow heat sinks to be attached to each step formed by a chip and the smaller chip above. An interface substrate sits at the bottom of the stack and provides for communication external to the stack by connecting the columns of chip to chip vias to an array of pins to mate with a connector. The short distances that signals must travel lends this three dimensional stacked chip package to high performance for off chip communications.

公开(公告)号：US6005253A

公开(公告)日：1999-12-21

申请号：US072002

申请日：1998-05-04

申请人： Sik On Kong

发明人： Sik On Kong

IPC分类号： H01J37/317 ,  H01L21/265 ,  H01L21/331 ,  H01J37/302

CPC分类号： H01L21/265 ,  H01J37/3171 ,  H01L21/26513 ,  H01L29/66272

摘要： A process is described for generating, through ion implantation, any desired concentration profile. This is accomplished by providing a set of mono-energetic doping concentration profiles which, when superimposed, generate the desired concentration profile (in a manner analogous to generating a square wave by superimposing multiple sine waves). The ion current, accelerating voltage, and dose needed to generate each member of the set is then computed and fed as input to software that controls the operation of the implanter. The various profiles from the set are then implemented while the ion beam remains stationary, thereby generating the desired profile at that spot. The beam is then moved to the next intended location and the process is repeated. In an alternative embodiment, each profile in the set is implemented over the entire surface scanned by the beam and then the process is successively repeated for the remaining members of the set.

摘要翻译： 描述了通过离子注入产生任何所需浓度分布的方法。 这通过提供一组单能量掺杂浓度分布来实现，当它们被叠加时，产生所需的浓度分布（以类似于通过叠加多个正弦波产生方波的方式）。 然后计算产生组的每个成员所需的离子电流，加速​​电压和剂量，并将其作为输入进给到控制注入机操作的软件。 然后在离子束保持静止的同时实现来自该组的各种轮廓，从而在该点产生期望的轮廓。 然后将光束移动到下一个预期位置，并重复该过程。 在替代实施例中，集合中的每个轮廓在由梁扫描的整个表面上实现，然后连续重复该组的剩余成员的过程。

公开(公告)号：US06759857B2

公开(公告)日：2004-07-06

申请号：US10256408

申请日：2002-09-27

申请人： Sik On Kong ,  Tsui Ping Chu

发明人： Sik On Kong ,  Tsui Ping Chu

IPC分类号： G01R31305

CPC分类号： G01N22/00 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new method and apparatus for detecting and measuring the level of metal present on the surface of a substrate is achieved. Energy, in the form of rf or light or microwave energy, is directed at the surface of a wafer, the reflected energy or the energy that passes through the semiconductor substrate is captured and analyzed for energy level and/or frequency content. Based on this analysis conclusions can be drawn regarding presence and type of metal on the surface of the wafer. Furthermore, by inclusion of metal within the resonating circuit of an rf generator changes the frequency of the vibration and therefore detects the presence of metal.

摘要翻译： 实现了用于检测和测量存在于基板表面上的金属的水平的新方法和装置。 以rf或光或微波能量的形式的能量被引导到晶片的表面，捕获并分析穿过半导体衬底的反射能量或能量来分析能级和/或频率内容。 基于该分析，可以得出关于晶片表面上的金属的存在和类型的结论。 此外，通过在rf发生器的谐振电路内包含金属来改变振动的频率，因此检测金属的存在。

公开(公告)号：US06538333B2

公开(公告)日：2003-03-25

申请号：US10167861

申请日：2002-06-11

申请人： Sik On Kong

发明人： Sik On Kong

IPC分类号： H01L2348

CPC分类号： H01L25/0657 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01019 ,  H01L2924/3011

摘要： In the present invention a high performance package is described where semiconductor chips are stacked together in a pancake like fashion with inter chip communications facilitated by chip to chip vias formed through the material of each chip. The chip to chip vias are created by etching and filling a hole from the back of a chip through the silicon substrate stopping at the first level of metalization and invoking the wiring of the chip to complete the path to the top side. The chip in the stack are aligned so that chip to chip vias form columns. Signal and power can travel the full length of a column from the bottom chip to the chip on top, or the wiring within the chips can interrupt the signal flow and form interstitial connections. Interstitial connections can also be used to enhance the wireability between chips in the stack. To accomodate cooling the chips in the stack are made in varying sizes and are ordered in size from the largest at the bottom of the stack to the smallest at the top of the stack. This provides a stair case like structure to allow heat sinks to be attached to each step formed by a chip and the smaller chip above. An interface substrate sits at the bottom of the stack and provides for communication external to the stack by connecting the columns of chip to chip vias to an array of pins to mate with a connector. The short distances that signals must travel lends this three dimensional stacked chip package to high performance for off chip communications.

摘要翻译： 在本发明中，描述了一种高性能封装，其中半导体芯片以类似薄饼的方式堆叠在一起，通过利用通过每个芯片的材料形成的芯片到芯片通孔来促进芯片间通信。 芯片到芯片通孔是通过在芯片的背面通过硅衬底进行蚀刻和填充孔而产生的，该硅衬底在第一金属化水平处停止并且调用芯片的布线以完成到顶侧的路径。 堆叠中的芯片对准，使得芯片到芯片通孔形成列。 信号和功率可以从底部芯片到芯片的顶部的行的全长行进，或者芯片内的接线可以中断信号流并形成间隙连接。 间隙连接也可用于增强堆叠中芯片之间的可线性。 为了适应冷却，堆叠中的芯片以不同的尺寸制成，并且从堆叠底部的最大尺寸到堆叠顶部的最小尺寸排列。 这提供了一种类似结构的台阶，以使散热片能够附着到由芯片和上述较小的芯片形成的每个步骤上。 接口基板位于堆叠的底部，并且通过将芯片列与芯片通孔连接到引脚阵列以与连接器配合来提供堆叠外部的通信。 信号必须行进的短距离将这种三维堆叠芯片封装提供给高性能的芯片外通信。

公开(公告)号：US6040996A

公开(公告)日：2000-03-21

申请号：US192337

申请日：1998-11-16

申请人： Sik On Kong

发明人： Sik On Kong

IPC分类号： G11C16/10 ,  G11C16/14 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3481 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3468

摘要： An EEPROM MOSFET memory device with a floating gate and control gate stack above source and drain regions formed in a substrate self-aligned with the stack. There is a means for writing data to the floating gate electrode by applying an upwardly stepwise increasing control gate voltage V.sub.CG1 waveform applied to the control gate of the EEPROM device. The waveform is a voltage ramp providing a substantially constant tunneling current into the floating gate electrode which is approximately constant with respect to time so programming speed and the number of write/erase cycles is increased. The means for threshold voltage testing compares the voltage of the drain electrode to a reference potential. The ramped pulse output is supplied to the control gate electrode by producing a sequence of increasingly higher counts to a decoder which provides sequential switching of successively higher voltage pulses from a voltage divider, and there is means for providing ramping programming voltages to the successively higher voltage pulses.

摘要翻译： 一种EEPROM MOSFET存储器件，其具有在与堆叠自对准的衬底中形成的源极和漏极区之上的浮动栅极和控制栅极堆叠。 通过施加向EEPROM器件的控制栅极施加的向上逐步增加的控制栅极电压VCG1波形，将数据写入浮栅电极。 该波形是电压斜坡，其提供了相对于时间大致恒定的浮动栅电极的基本恒定的隧穿电流，因此编程速度和写入/擦除周期的数量增加。 用于阈值电压测试的方法将漏电极的电压与参考电位进行比较。 斜坡脉冲输出通过对解码器产生越来越高的计数的序列来提供给控制栅极电极，解码器提供来自分压器的连续更高电压脉冲的顺序切换，并且存在用于向连续更高电压提供斜坡编程电压的装置 脉冲。

公开(公告)号：US06815239B1

公开(公告)日：2004-11-09

申请号：US09262000

申请日：1999-03-05

申请人： Sik On Kong ,  Rajan Rajgopal ,  George Wong

发明人： Sik On Kong ,  Rajan Rajgopal ,  George Wong

IPC分类号： H01L2100

CPC分类号： G02F1/13394 ,  G02F1/133553 ,  G02F1/136277

摘要： Five new methods for the formation of an improved liquid-crystal-on-silicon display are described, in which the device structure is enhanced by the photolithographic building of alignment posts among the mirror pixels of the micro-display. These five methods accommodate the fabrication of an optical interference multilayer, which improves the image quality of the reflected light. These five methods are: Silicon Dioxide Posts by Wet Etching. Amorphous Silicon Posts by Plasma Etching. Silicon Nitride Posts by Plug Filling. Insulation Material Posts by Lift-off. Polyimide Posts by Photosensitive Etching.

摘要翻译： 描述了用于形成改进的液晶显示器的五种新方法，其中通过微显示器的反射镜像素中的对准柱的光刻建筑来增强器件结构。 这五种方法适应光学干涉多层的制造，这提高了反射光的图像质量。 这五种方法是：湿法蚀刻二氧化硅柱。等离子体蚀刻的非晶硅柱。通过插塞填充的氮化硅柱。通过光敏蚀刻剥离聚酰亚胺柱的绝缘材料柱。