Tool Induced Shift Reduction Determination for Overlay Metrology
    1.
    发明申请
    Tool Induced Shift Reduction Determination for Overlay Metrology 有权
    刀具诱导换位测量用于覆盖计量学

    公开(公告)号:US20130286395A1

    公开(公告)日:2013-10-31

    申请号:US13457832

    申请日:2012-04-27

    IPC分类号: G01B11/00

    CPC分类号: G01B11/00 G03F7/70633

    摘要: One embodiment relates to a method for semiconductor workpiece processing. In this method, a baseline tool induced shift (TIS) is measured by performing a baseline number of TIS measurements on a first semiconductor workpiece. After the baseline TIS has been determined, the method determines a subsequent TIS based on a subsequent number of TIS measurements taken on a first subsequent semiconductor workpiece. The subsequent number of TIS measurements is less than the baseline number of TIS measurements.

    摘要翻译: 一个实施例涉及一种用于半导体工件加工的方法。 在该方法中,通过在第一半导体工件上执行TIS测量的基线数量来测量基线工具诱发位移(TIS)。 在确定基线TIS之后,该方法基于在第一后续半导体工件上进行的随后的TIS测量数确定随后的TIS。 随后的TIS测量数量小于TIS测量的基线数量。

    Tool induced shift reduction determination for overlay metrology
    2.
    发明授权
    Tool induced shift reduction determination for overlay metrology 有权
    刀具诱导移位减少确定重叠度量

    公开(公告)号:US08860941B2

    公开(公告)日:2014-10-14

    申请号:US13457832

    申请日:2012-04-27

    IPC分类号: G01B11/00

    CPC分类号: G01B11/00 G03F7/70633

    摘要: One embodiment relates to a method for semiconductor workpiece processing. In this method, a baseline tool induced shift (TIS) is measured by performing a baseline number of TIS measurements on a first semiconductor workpiece. After the baseline TIS has been determined, the method determines a subsequent TIS based on a subsequent number of TIS measurements taken on a first subsequent semiconductor workpiece. The subsequent number of TIS measurements is less than the baseline number of TIS measurements.

    摘要翻译: 一个实施例涉及一种用于半导体工件加工的方法。 在该方法中,通过在第一半导体工件上执行TIS测量的基线数量来测量基线工具诱发位移(TIS)。 在确定基线TIS之后,该方法基于在第一后续半导体工件上进行的随后的TIS测量数确定随后的TIS。 随后的TIS测量数量小于TIS测量的基线数量。

    Enhanced scanner throughput system and method
    4.
    发明授权
    Enhanced scanner throughput system and method 有权
    增强扫描仪吞吐量系统和方法

    公开(公告)号:US08906599B2

    公开(公告)日:2014-12-09

    申请号:US13473695

    申请日:2012-05-17

    IPC分类号: G03F7/20

    CPC分类号: G03F7/70358

    摘要: A method and system to improve scanner throughput is provided. An image from a reticle is projected onto a substrate using a continuous linear scanning procedure in which an entire column of die or cells of die is scanned continuously, i.e. without stepping to a different location. Each scan includes translating a substrate with respect to a fixed beam. While the substrate is translated, the reticle is also translated. When a first die or cell of die is projected onto the substrate, the reticle translates along a direction opposite the scan direction and as the scan continues along the same direction, the reticle then translates in the opposite direction of the substrate thereby forming an inverted pattern on the next die or cell. The time associated with exposing the substrate is minimized as the stepping operation only occurs after a complete column of cells is scanned.

    摘要翻译: 提供了一种提高扫描仪吞吐量的方法和系统。 使用连续线性扫描程序将来自掩模版的图像投影到基板上,其中连续扫描整列管芯或裸片的单元,即不进入不同的位置。 每个扫描包括相对于固定光束平移衬底。 当底物被翻译时,掩模版也被翻译。 当模具的第一裸片或裸片投影到衬底上时,标线沿着与扫描方向相反的方向平移,并且随着扫描沿着相同的方向继续,标线片然后沿着衬底的相反方向平移,从而形成倒置图案 在下一个死亡或细胞。 与曝光底物相关的时间最小化,因为步进操作仅在扫描完整的单元格列之后才发生。

    Wafer edge exposure unit
    6.
    发明授权
    Wafer edge exposure unit 有权
    晶圆边缘曝光单元

    公开(公告)号:US07901854B2

    公开(公告)日:2011-03-08

    申请号:US12437776

    申请日:2009-05-08

    CPC分类号: G03B27/62 G03F7/70425

    摘要: A wafer edge exposure unit comprises a chuck for supporting a wafer. The chuck is rotatable about a central axis. A plurality of light sources are positioned or movably positionable with a common radial distance from the axis of the rotatable chuck, each light source configured to direct exposure light on a respective edge portion of the wafer simultaneously.

    摘要翻译: 晶片边缘曝光单元包括用于支撑晶片的卡盘。 卡盘可绕中心轴线旋转。 多个光源以可旋转卡盘的轴线的公共径向距离定位或可移动地定位,每个光源被配置为将曝光光同时引导到晶片的相应边缘部分。

    Litho cluster and modulization to enhance productivity
    7.
    发明授权
    Litho cluster and modulization to enhance productivity 有权
    Litho集群和模块化以提高生产力

    公开(公告)号:US08903532B2

    公开(公告)日:2014-12-02

    申请号:US13429921

    申请日:2012-03-26

    IPC分类号: H01L31/18

    摘要: The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.

    摘要翻译: 本公开涉及一种用于半导体工件加工的平版印刷工具装置。 光刻工具装置将光刻工具组合成簇,并且将半导体工件在第一簇中的第一类型的多个光刻工具之间选择性地传输到第二簇中的第二类型的光刻工具。 通过转移组件实现选择性转移,转移组件耦合到识别第一类型的光刻工具中产生的缺陷的缺陷扫描工具。 所公开的平版印刷工具装置还利用共同的结构元件,例如壳体组件和诸如气体和化学品的共享功能元件。 光刻工具装置可以包括被配置成提供这些各种部件的模块化的烘烤,涂覆,曝光和显影单元,以便为给定的光刻制造工艺优化产量和效率。

    Litho Cluster and Modulization to Enhance Productivity
    8.
    发明申请
    Litho Cluster and Modulization to Enhance Productivity 有权
    Litho集群和模块化以提高生产力

    公开(公告)号:US20130252175A1

    公开(公告)日:2013-09-26

    申请号:US13429921

    申请日:2012-03-26

    IPC分类号: G03F7/20 H01L21/00

    摘要: The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.

    摘要翻译: 本公开涉及一种用于半导体工件加工的平版印刷工具装置。 光刻工具装置将光刻工具组合成簇,并且将半导体工件在第一簇中的第一类型的多个光刻工具之间选择性地传输到第二簇中的第二类型的光刻工具。 通过转移组件实现选择性转移,转移组件耦合到识别第一类型的光刻工具中产生的缺陷的缺陷扫描工具。 所公开的平版印刷工具装置还利用共同的结构元件,例如壳体组件和诸如气体和化学品的共享功能元件。 光刻工具装置可以包括被配置成提供这些各种部件的模块化的烘烤,涂覆,曝光和显影单元,以便为给定的光刻制造工艺优化产量和效率。

    WAFER EDGE EXPOSURE UNIT
    9.
    发明申请
    WAFER EDGE EXPOSURE UNIT 有权
    WAFER EDGE曝光单元

    公开(公告)号:US20100285399A1

    公开(公告)日:2010-11-11

    申请号:US12437776

    申请日:2009-05-08

    IPC分类号: G03F7/20 G03B27/62

    CPC分类号: G03B27/62 G03F7/70425

    摘要: A wafer edge exposure unit comprises a chuck for supporting a wafer. The chuck is rotatable about a central axis. A plurality of light sources are positioned or movably positionable with a common radial distance from the axis of the rotatable chuck, each light source configured to direct exposure light on a respective edge portion of the wafer simultaneously.

    摘要翻译: 晶片边缘曝光单元包括用于支撑晶片的卡盘。 卡盘可绕中心轴线旋转。 多个光源以可旋转卡盘的轴线的公共径向距离定位或可移动地定位,每个光源被配置为将曝光光同时引导到晶片的相应边缘部分。

    Structure of stacking scatterometry based overlay marks for marks footprint reduction
    10.
    发明授权
    Structure of stacking scatterometry based overlay marks for marks footprint reduction 有权
    基于堆叠散射法的覆盖标记的结构,用于标记尺寸减少

    公开(公告)号:US08183701B2

    公开(公告)日:2012-05-22

    申请号:US12511638

    申请日:2009-07-29

    IPC分类号: H01L23/544 H01L21/00

    摘要: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch.

    摘要翻译: 本发明提供集成电路。 集成电路包括半导体衬底; 形成在所述半导体基板上的多个材料层,每个所述材料层包括其中的电路图案; 以及形成在多个材料层中并堆叠在相同区域中的多个衍射基周期标记。 基于衍射的周期标记中的一个不同于间距中基于衍射的周期性标记中的至少另一个。