公开(公告)号：US20100285399A1

公开(公告)日：2010-11-11

申请号：US12437776

申请日：2009-05-08

申请人： Po-Chang Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee

发明人： Po-Chang Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee

IPC分类号： G03F7/20 ,  G03B27/62

CPC分类号： G03B27/62 ,  G03F7/70425

摘要： A wafer edge exposure unit comprises a chuck for supporting a wafer. The chuck is rotatable about a central axis. A plurality of light sources are positioned or movably positionable with a common radial distance from the axis of the rotatable chuck, each light source configured to direct exposure light on a respective edge portion of the wafer simultaneously.

摘要翻译： 晶片边缘曝光单元包括用于支撑晶片的卡盘。 卡盘可绕中心轴线旋转。 多个光源以可旋转卡盘的轴线的公共径向距离定位或可移动地定位，每个光源被配置为将曝光光同时引导到晶片的相应边缘部分。

公开(公告)号：US07901854B2

公开(公告)日：2011-03-08

申请号：US12437776

申请日：2009-05-08

申请人： Po-Chang Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee

发明人： Po-Chang Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee

IPC分类号： G03F9/00 ,  G03C5/00 ,  G03B27/32 ,  G03B27/42

CPC分类号： G03B27/62 ,  G03F7/70425

摘要： A wafer edge exposure unit comprises a chuck for supporting a wafer. The chuck is rotatable about a central axis. A plurality of light sources are positioned or movably positionable with a common radial distance from the axis of the rotatable chuck, each light source configured to direct exposure light on a respective edge portion of the wafer simultaneously.

摘要翻译： 晶片边缘曝光单元包括用于支撑晶片的卡盘。 卡盘可绕中心轴线旋转。 多个光源以可旋转卡盘的轴线的公共径向距离定位或可移动地定位，每个光源被配置为将曝光光同时引导到晶片的相应边缘部分。

公开(公告)号：US08903532B2

公开(公告)日：2014-12-02

申请号：US13429921

申请日：2012-03-26

申请人： I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

发明人： I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

IPC分类号： H01L31/18

CPC分类号： G03F7/30 ,  G03F7/16 ,  G03F7/70991 ,  H01L21/67225 ,  H01L21/67745

摘要： The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.

摘要翻译： 本公开涉及一种用于半导体工件加工的平版印刷工具装置。 光刻工具装置将光刻工具组合成簇，并且将半导体工件在第一簇中的第一类型的多个光刻工具之间选择性地传输到第二簇中的第二类型的光刻工具。 通过转移组件实现选择性转移，转移组件耦合到识别第一类型的光刻工具中产生的缺陷的缺陷扫描工具。 所公开的平版印刷工具装置还利用共同的结构元件，例如壳体组件和诸如气体和化学品的共享功能元件。 光刻工具装置可以包括被配置成提供这些各种部件的模块化的烘烤，涂覆，曝光和显影单元，以便为给定的光刻制造工艺优化产量和效率。

公开(公告)号：US20130286395A1

公开(公告)日：2013-10-31

申请号：US13457832

申请日：2012-04-27

申请人： Yung-Yao Lee ,  Ying Ying Wang ,  Heng-Hsin Liu ,  Heng-Jen Lee

发明人： Yung-Yao Lee ,  Ying Ying Wang ,  Heng-Hsin Liu ,  Heng-Jen Lee

IPC分类号： G01B11/00

CPC分类号： G01B11/00 ,  G03F7/70633

摘要： One embodiment relates to a method for semiconductor workpiece processing. In this method, a baseline tool induced shift (TIS) is measured by performing a baseline number of TIS measurements on a first semiconductor workpiece. After the baseline TIS has been determined, the method determines a subsequent TIS based on a subsequent number of TIS measurements taken on a first subsequent semiconductor workpiece. The subsequent number of TIS measurements is less than the baseline number of TIS measurements.

摘要翻译： 一个实施例涉及一种用于半导体工件加工的方法。 在该方法中，通过在第一半导体工件上执行TIS测量的基线数量来测量基线工具诱发位移（TIS）。 在确定基线TIS之后，该方法基于在第一后续半导体工件上进行的随后的TIS测量数确定随后的TIS。 随后的TIS测量数量小于TIS测量的基线数量。

公开(公告)号：US20130252175A1

公开(公告)日：2013-09-26

申请号：US13429921

申请日：2012-03-26

申请人： I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

发明人： I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

IPC分类号： G03F7/20 ,  H01L21/00

CPC分类号： G03F7/30 ,  G03F7/16 ,  G03F7/70991 ,  H01L21/67225 ,  H01L21/67745

摘要： The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process.

摘要翻译： 本公开涉及一种用于半导体工件加工的平版印刷工具装置。 光刻工具装置将光刻工具组合成簇，并且将半导体工件在第一簇中的第一类型的多个光刻工具之间选择性地传输到第二簇中的第二类型的光刻工具。 通过转移组件实现选择性转移，转移组件耦合到识别第一类型的光刻工具中产生的缺陷的缺陷扫描工具。 所公开的平版印刷工具装置还利用共同的结构元件，例如壳体组件和诸如气体和化学品的共享功能元件。 光刻工具装置可以包括被配置成提供这些各种部件的模块化的烘烤，涂覆，曝光和显影单元，以便为给定的光刻制造工艺优化产量和效率。

公开(公告)号：US08860941B2

公开(公告)日：2014-10-14

申请号：US13457832

申请日：2012-04-27

申请人： Yung-Yao Lee ,  Ying Ying Wang ,  Heng-Hsin Liu ,  Heng-Jen Lee

发明人： Yung-Yao Lee ,  Ying Ying Wang ,  Heng-Hsin Liu ,  Heng-Jen Lee

IPC分类号： G01B11/00

CPC分类号： G01B11/00 ,  G03F7/70633

摘要： One embodiment relates to a method for semiconductor workpiece processing. In this method, a baseline tool induced shift (TIS) is measured by performing a baseline number of TIS measurements on a first semiconductor workpiece. After the baseline TIS has been determined, the method determines a subsequent TIS based on a subsequent number of TIS measurements taken on a first subsequent semiconductor workpiece. The subsequent number of TIS measurements is less than the baseline number of TIS measurements.

摘要翻译： 一个实施例涉及一种用于半导体工件加工的方法。 在该方法中，通过在第一半导体工件上执行TIS测量的基线数量来测量基线工具诱发位移（TIS）。 在确定基线TIS之后，该方法基于在第一后续半导体工件上进行的随后的TIS测量数确定随后的TIS。 随后的TIS测量数量小于TIS测量的基线数量。

公开(公告)号：US08183701B2

公开(公告)日：2012-05-22

申请号：US12511638

申请日：2009-07-29

申请人： Chi-Yuan Shih ,  Sophia Wang ,  Heng-Hsin Liu ,  Heng-Jen Lee

发明人： Chi-Yuan Shih ,  Sophia Wang ,  Heng-Hsin Liu ,  Heng-Jen Lee

IPC分类号： H01L23/544 ,  H01L21/00

CPC分类号： G03F9/7049 ,  G03F7/70625 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/7084

摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch.

摘要翻译： 本发明提供集成电路。 集成电路包括半导体衬底; 形成在所述半导体基板上的多个材料层，每个所述材料层包括其中的电路图案; 以及形成在多个材料层中并堆叠在相同区域中的多个衍射基周期标记。 基于衍射的周期标记中的一个不同于间距中基于衍射的周期性标记中的至少另一个。

公开(公告)号：US20110076843A1

公开(公告)日：2011-03-31

申请号：US12566853

申请日：2009-09-25

申请人： I-Hsiung Huang ,  Chin-Hsiang Lin ,  Heng-Jen Lee ,  Heng-Hsin Liu

发明人： I-Hsiung Huang ,  Chin-Hsiang Lin ,  Heng-Jen Lee ,  Heng-Hsin Liu

IPC分类号： H01L21/28 ,  H01L21/302

CPC分类号： H01L21/823871 ,  G03F7/091 ,  G03F7/093 ,  G03F7/11 ,  Y10S438/942

摘要： A method for fabricating an integrated circuit device is disclosed. The method is a lithography patterning method that can include providing a substrate; forming a protective layer over the substrate; forming a conductive layer over the protective layer; forming a resist layer over the conductive layer; and exposing and developing the resist layer.

摘要翻译： 公开了一种用于制造集成电路器件的方法。 该方法是可以包括提供衬底的光刻图案化方法; 在衬底上形成保护层; 在保护层上形成导电层; 在导电层上形成抗蚀剂层; 并且曝光和显影抗蚀剂层。

公开(公告)号：US20110024924A1

公开(公告)日：2011-02-03

申请号：US12511638

申请日：2009-07-29

申请人： Chi-Yuan Shih ,  Sophia Wang ,  Heng-Hsin Liu ,  Heng-Jen Lee

发明人： Chi-Yuan Shih ,  Sophia Wang ,  Heng-Hsin Liu ,  Heng-Jen Lee

IPC分类号： H01L23/544 ,  H01L21/66

CPC分类号： G03F9/7049 ,  G03F7/70625 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/7084

摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; a plurality of material layers formed on the semiconductor substrate, each of the material layers including a circuit pattern therein; and a plurality of diffraction-based periodic marks formed in the plurality of material layers and stacked in a same region. One of the diffraction-based periodic marks is different from at least one other of the diffraction-based periodic marks in pitch.

摘要翻译： 本发明提供集成电路。 集成电路包括半导体衬底; 形成在所述半导体基板上的多个材料层，每个所述材料层包括其中的电路图案; 以及形成在多个材料层中并堆叠在相同区域中的多个衍射基周期标记。 基于衍射的周期标记中的一个不同于间距中基于衍射的周期性标记中的至少另一个。

公开(公告)号：US09111982B2

公开(公告)日：2015-08-18

申请号：US13539243

申请日：2012-06-29

申请人： I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

发明人： I-Hsiung Huang ,  Heng-Hsin Liu ,  Heng-Jen Lee ,  Chin-Hsiang Lin

IPC分类号： H01L21/683

CPC分类号： H01L21/0201 ,  H01L21/6835 ,  H01L2221/6834 ,  H01L2221/68381

摘要： A wafer assembly includes a process wafer and a carrier wafer. Integrated circuits are formed on the process wafer. The carrier wafer is bonded to the process wafer. The carrier wafer has at least one alignment mark.

摘要翻译： 晶片组件包括处理晶片和载体晶片。 集成电路形成在处理晶片上。 载体晶片结合到工艺晶片。 载体晶片具有至少一个对准标记。