公开(公告)号：US10178776B2

公开(公告)日：2019-01-08

申请号：US15529183

申请日：2015-05-13

Applicant: ZTE CORPORATION

Inventor： Tao Guo ,  Fengchao Ma ,  Yuanwang Zhang

IPC: H05K1/02 ,  H05K3/10 ,  H05K1/03

Abstract: A method for wiring differential signal lines and a PCB are disclosed. The wiring method includes: providing a rectangle-shaped glass fiber fabric formed of glass fibers which are woven and interlaced with each other and an adhesive filled therebetween; determining a wiring direction and obtaining a glass fiber bundle number of the glass fiber fabric in the wiring direction; equally dividing the glass fiber fabric into glass fiber units, and obtaining a width of each glass fiber unit according to a size of the glass fiber fabric in a direction perpendicular to the wiring direction and the number of the glass fiber units; determining a line distance and line widths of the differential signal lines; and according to the line distance and the line widths, forming the differential signal lines on a metal layer along the wiring direction to make the differential signal lines meet predetermined requirements.

公开(公告)号：US10064271B2

公开(公告)日：2018-08-28

申请号：US15108405

申请日：2014-05-21

Applicant: ZTE CORPORATION

Inventor： Bi Yi ,  Fengchao Ma ,  Yonghui Ren ,  Wang Xiong ,  Yingxin Wang

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/46 ,  H05K1/11 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/10303 ,  H05K2203/0207 ,  H05K2203/16

Abstract: The present disclosure discloses a PCB processing method and a PCB. The method includes: respectively carrying out laminating processing on a plurality of PCB daughter boards constituting a PCB, and drilling and electroplating the top-most PCB daughter board to form a via hole; and laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By virtue of the technical scheme of the present disclosure, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.