公开(公告)号：US20160323995A1

公开(公告)日：2016-11-03

申请号：US15108405

申请日：2014-05-21

Applicant: ZTE CORPORATION

Inventor： Bi YI ,  Fengchao MA ,  Yonghui REN ,  Wang XIONG ,  Yingxin WANG

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/46 ,  H05K1/11 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/10303 ,  H05K2203/0207 ,  H05K2203/16

Abstract: The present disclosure discloses a PCB processing method and a PCB. The method includes: respectively carrying out laminating processing on a plurality of PCB daughter boards constituting a PCB, and drilling and electroplating the top-most PCB daughter board to form a via hole; and laminating the plurality of PCB daughter boards together to form the PCB, and drilling and electroplating the formed PCB to form a through hole for mounting a connector, wherein a blind hole for mounting a connector is formed by the via hole, and a depth of the blind hole is greater than or equal to the length of a signal pin of the connector. By virtue of the technical scheme of the present disclosure, a space between wafers of the lower layer of PCBs may be doubled, and the space for layout between wafers may be doubled.

Abstract translation: 本公开公开了一种PCB处理方法和PCB。 该方法包括：分别在构成PCB的多个PCB子板上进行层压处理，以及对最顶层的PCB​​子板进行钻孔和电镀以形成通孔; 并且将多个PCB子板层压在一起以形成PCB，并且对所形成的PCB进行钻孔和电镀以形成用于安装连接器的通孔，其中用于安装连接器的盲孔由通孔形成，并且深度 盲孔大于或等于连接器的信号针的长度。 由于本公开的技术方案，PCB的下层的晶片之间的间隔可以加倍，并且晶片之间的布局空间可以加倍。

公开(公告)号：US20210392744A1

公开(公告)日：2021-12-16

申请号：US17282410

申请日：2019-09-27

Applicant: ZTE CORPORATION

Inventor： Changgang YIN ,  Yingxin WANG ,  Bi YI ,  Huazhang CAO

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/42

Abstract: Provided are a circuit board, an apparatus and a method for forming a via hole structure. A via hole structure formed on a main body (10) of a circuit board includes a hole (12) enclosed by a conductive layer in the main body (10), the conductive layer constitutes a wall (11) of the hole (12), and a dielectric filling layer (13), which has a dielectric constant smaller than that of the main body (10), is disposed between at least a portion of the wall (11) of the hole (12) and the main body (10), so that the parasitic capacitance of a via hole is decreased, and the impedance of the via hole is increased to become closer to the impedance of a transmission line, thereby effectively improving impedance continuity of a system link.

公开(公告)号：US20220100945A1

公开(公告)日：2022-03-31

申请号：US17417877

申请日：2019-10-14

Applicant: ZTE Corporation

Inventor： Xinjian CHEN ,  Yonghui REN ,  Rongxing BAN ,  Yingxin WANG

IPC: G06F30/394 ,  G06F13/40

Abstract: Provided are a connector structure, and a skew calculation method and device. Specifically, the connector structure includes: a first Printed Circuit Board (PCB) (12), which includes a first board (122) and a second board (124), and is connected to a testing device; and a second PCB (14), which includes a third board (142) and a fourth board (144), and is connected to the testing device. The first board (122) is connected to the third board (142) through a connector (16).

公开(公告)号：US20210092830A1

公开(公告)日：2021-03-25

申请号：US17106069

申请日：2020-11-27

Applicant: ZTE CORPORATION

Inventor： Changgang YIN ,  Huazhang CAO ,  Yingxin WANG

IPC: H05K1/02

Abstract: Provided is a circuit board, a signal crosstalk suppression method, a storage medium and an electronic device. The circuit board includes: a circuit board body, provided with a signal via-hole structure, a ground via-hole structure and a slotted structure; the signal via-hole structure is configured to transmit a signal by changing a layer, and the ground via-hole structure is configured to return a signal transmitted from the signal via-hole structure; the slotted structure is provided between the signal via-hole structure and the ground via-hole structure, and configured to suppress a signal crosstalk of the signal via-hole structure.