公开(公告)号：US06215151B1

公开(公告)日：2001-04-10

申请号：US09255667

申请日：1999-02-23

申请人： Zhiqiang Wu ,  Luan C. Tran ,  Robert Kerr ,  Shubneesh Batra ,  Rongsheng Yang

发明人： Zhiqiang Wu ,  Luan C. Tran ,  Robert Kerr ,  Shubneesh Batra ,  Rongsheng Yang

IPC分类号： H01L27148

CPC分类号： H01L21/823807

摘要： Integrated circuitry and methods of forming integrated circuitry are described. In one implementation, a common masking step is utilized to provide source/drain diffusion regions and halo ion implantation or dopant regions relative to the source/drain regions within one well region of a substrate; and well contact diffusion regions within another well region of the substrate. The common masking step preferably defines at least one mask opening over the substrate within which the well contact diffusion region is to be formed, and the mask opening is suitably dimensioned to reduce the amount of halo ion implantation dopant which ultimately reaches the substrate therebelow. According to one aspect, a plurality of mask openings are provided. According to another aspect, a suitably-dimensioned single mask opening is provided. In yet another aspect, a unique well region construction is provided with one or more complementary mask openings which is (are) configured to, in connection with the provision of the halo ion implantation dopant, block the amount of implantation dopant which ultimately reaches the substrate adjacent the well contact diffusion regions. Accordingly, at least some of the well contact diffusion region(s) remain in substantial contact with the well region after the doping of the substrate with the halo ion implantation dopant.

摘要翻译： 描述了形成集成电路的集成电路和方法。 在一个实现中，利用公共掩模步骤来相对于衬底的一个阱区域内的源极/漏极区域提供源极/漏极扩散区域和晕圈离子注入或掺杂区域; 以及在衬底的另一个阱区域内的良好接触扩散区域。 常见的掩蔽步骤优选地限定在其上将要形成阱接触扩散区的衬底上的至少一个掩模开口，并且掩模开口被适当地设定尺寸以减少最终到达衬底的卤素离子注入掺杂剂的量。 根据一个方面，提供了多个掩模开口。 根据另一方面，提供了适当尺寸的单个掩模开口。 在另一方面，独特的井区结构设置有一个或多个互补掩模开口，其被配置为与提供卤素离子注入掺杂剂相结合，阻止最终到达衬底的注入掺杂剂的量 邻近阱接触扩散区。 因此，在用卤素离子注入掺杂剂掺杂衬底之后，至少一些阱接触扩散区域保持与阱区基本接触。

公开(公告)号：US5946564A

公开(公告)日：1999-08-31

申请号：US912108

申请日：1997-08-04

申请人： Zhiqiang Wu ,  Luan C. Tran ,  Robert Kerr ,  Shubneesh Batra ,  Rongsheng Yang

发明人： Zhiqiang Wu ,  Luan C. Tran ,  Robert Kerr ,  Shubneesh Batra ,  Rongsheng Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807

摘要： Integrated circuitry and methods of forming integrated circuitry are described. In one implementation, a common masking step is utilized to provide source/drain diffusion regions and halo ion implantation or dopant regions relative to the source/drain regions within one well region of a substrate; and well contact diffusion regions within another well region of the substrate. The common masking step preferably defines at least one mask opening over the substrate within which the well contact diffusion region is to be formed, and the mask opening is suitably dimensioned to reduce the amount of halo ion implantation dopant which ultimately reaches the substrate therebelow. According to one aspect, a plurality of mask openings are provided. According to another aspect, a suitably-dimensioned single mask opening is provided. In yet another aspect, a unique well region construction is provided with one or more complementary mask openings which is (are) configured to, in connection with the provision of the halo ion implantation dopant, block the amount of implantation dopant which ultimately reaches the substrate adjacent the well contact diffusion regions. Accordingly, at least some of the well contact diffusion region(s) remain in substantial contact with the well region after the doping of the substrate with the halo ion implantation dopant.

摘要翻译： 描述了形成集成电路的集成电路和方法。 在一个实现中，利用公共掩模步骤来相对于衬底的一个阱区域内的源极/漏极区域提供源极/漏极扩散区域和晕圈离子注入或掺杂区域; 以及在衬底的另一个阱区域内的良好接触扩散区域。 常见的掩蔽步骤优选地限定在其上将要形成阱接触扩散区的衬底上的至少一个掩模开口，并且掩模开口被适当地设定尺寸以减少最终到达衬底的卤素离子注入掺杂剂的量。 根据一个方面，提供了多个掩模开口。 根据另一方面，提供了适当尺寸的单个掩模开口。 在另一方面，独特的井区结构设置有一个或多个互补掩模开口，其被配置为与提供卤素离子注入掺杂剂相结合，阻止最终到达衬底的注入掺杂剂的量 邻近阱接触扩散区。 因此，在用卤素离子注入掺杂剂掺杂衬底之后，至少一些阱接触扩散区域保持与阱区基本接触。

公开(公告)号：US06406954B1

公开(公告)日：2002-06-18

申请号：US09388559

申请日：1999-09-02

申请人： Shubneesh Batra ,  Luan C. Tran ,  Tyler A. Lowrey

发明人： Shubneesh Batra ,  Luan C. Tran ,  Tyler A. Lowrey

IPC分类号： H01L218238

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： In one aspect, the invention includes a semiconductor processing method of diffusing dopant into both n-type and p-type doped regions of a semiconductive substrate. A semiconductive material is provided. The semiconductive material has a first portion and a second portion. The first portion is a p-type doped portion and the second portion is an n-type doped portion. A mask material is formed over the p-type and n-type doped portions. A first opening is formed to extend through the mask material and to the n-type doped portion. A second opening is formed to extend through the mask material and to the p-type doped portion. Conductively doped polysilicon is formed within the first and second openings. Dopant is out-diffused from the conductively-doped polysilicon and into the n-type and p-type doped portions. In another aspect, the invention includes methods of forming CMOS constructions. In yet another aspect, the invention encompasses methods of forming DRAM constructions.

摘要翻译： 一方面，本发明包括将掺杂剂扩散到半导体衬底的n型和p型掺杂区域中的半导体处理方法。 提供半导体材料。 半导体材料具有第一部分和第二部分。 第一部分是p型掺杂部分，第二部分是n型掺杂部分。 在p型和n型掺杂部分上形成掩模材料。 形成第一开口以延伸穿过掩模材料和n型掺杂部分。 形成第二开口以延伸穿过掩模材料和p型掺杂部分。 导电掺杂多晶硅形成在第一和第二开口内。 掺杂剂从导电掺杂多晶硅扩散到n型和p型掺杂部分。 另一方面，本发明包括形成CMOS结构的方法。 在另一方面，本发明包括形成DRAM结构的方法。

公开(公告)号：US06784502B2

公开(公告)日：2004-08-31

申请号：US09512978

申请日：2000-02-24

申请人： Robert Kerr ,  Brian Shirley ,  Luan C. Tran ,  Tyler A. Lowrey

发明人： Robert Kerr ,  Brian Shirley ,  Luan C. Tran ,  Tyler A. Lowrey

IPC分类号： H01L2976

CPC分类号： H01L27/10897 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/10891 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration. In operation, the pn junction is sufficiently biased to preclude electrical shorting between the conductive line and the substrate for selected magnitudes of electrical current provided through the conductive line and the conductive material forming the conductive contacts.

摘要翻译： 描述形成触点的方法，接触线的方法，操作集成电路的方法以及相关的集成电路结构。 在一个实施例中，多个导电线形成在衬底之上，扩散区形成在衬底正下方的线下方。 单独的扩散区域设置在各个导电线部分附近，并且与其共同地限定需要电连接的各个接触焊盘。 绝缘材料形成在导电线部分和扩散区域上，其中接触开口穿过其形成以暴露各个接触焊盘的部分。 导电触点形成在接触开口内并与各个接触垫电连接。 在优选实施例中，衬底和扩散区域提供pn结，其被配置为偏置成反向偏置二极管配置。 在操作中，pn结被充分地偏置，以防止导电线和衬底之间的电短路，用于通过导电线和形成导电触点的导电材料提供的选定大小的电流。

公开(公告)号：US06380023B2

公开(公告)日：2002-04-30

申请号：US09146115

申请日：1998-09-02

申请人： Robert Kerr ,  Brian Shirley ,  Luan C. Tran ,  Tyler A. Lowrey

发明人： Robert Kerr ,  Brian Shirley ,  Luan C. Tran ,  Tyler A. Lowrey

IPC分类号： H01L218234

CPC分类号： H01L27/10897 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/10891 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration. In operation, the pn junction is sufficiently biased to preclude electrical shorting between the conductive line and the substrate for selected magnitudes of electrical current provided through the conductive line and the conductive material forming the conductive contacts.

摘要翻译： 描述形成触点的方法，接触线的方法，操作集成电路的方法以及相关的集成电路结构。 在一个实施例中，多个导电线形成在衬底之上，扩散区形成在衬底正下方的线下方。 单独的扩散区域设置在各个导电线部分附近，并且与其共同地限定需要电连接的各个接触焊盘。 绝缘材料形成在导电线部分和扩散区域上，其中接触开口穿过其形成以暴露各个接触焊盘的部分。 导电触点形成在接触开口内并与各个接触垫电连接。 在优选实施例中，衬底和扩散区域提供pn结，其被配置为偏置成反向偏置二极管配置。 在操作中，pn结被充分地偏置，以防止导电线和衬底之间的电短路，用于通过导电线和形成导电触点的导电材料提供的选定大小的电流。

公开(公告)号：US06759288B2

公开(公告)日：2004-07-06

申请号：US10208830

申请日：2002-08-01

申请人： Luan C. Tran ,  Mark McQueen ,  Robert Kerr

发明人： Luan C. Tran ,  Mark McQueen ,  Robert Kerr

IPC分类号： H01L21337

CPC分类号： H01L27/10894 ,  H01L27/10897 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： An integrated circuit device with improved DRAM refresh characteristics, and a novel method of making the device, is provided. A semiconductor substrate is provided with gate structures formed on its surface in each of an array portion and a peripheral portion. Single lightly doped regions are formed adjacent to the channel regions by ion implantation in the substrate. Dielectric spacers having a first width are formed on the substrate surface adjacent to the gate structures covering at least a portion of the single lightly doped regions. Heavily-doped regions are ion-implanted on opposite sides of the gate structure in the peripheral portion. The dielectric spacers are etched back to a second width smaller than the first width. Double lightly doped regions are formed by ion implantation in the substrate in an area of the substrate left exposed by the spacer etch back. Triple lightly doped regions may be also be formed by a first implant at the gate edge, a second implant through an intermediate spacer, and a third implant after the spacer etch back.

摘要翻译： 提供了具有改进的DRAM刷新特性的集成电路器件，以及制造该器件的新颖方法。 半导体基板在阵列部分和周边部分中的表面上设置有栅极结构。 单个轻掺杂区域通过在衬底中的离子注入形成在沟道区附近。 具有第一宽度的电介质间隔物形成在与覆盖单个轻掺杂区域的至少一部分的栅极结构相邻的衬底表面上。 重掺杂区域被离子注入在外围部分中的栅极结构的相对侧上。 电介质间隔物被回蚀到小于第一宽度的第二宽度。 通过离子注入形成双重轻掺杂区域，该衬底在衬底的由间隔物回蚀刻暴露的区域中。 三个轻掺杂区域也可以通过在栅极边缘处的第一注入，通过中间间隔物的第二植入物和间隔物回蚀后的第三植入物形成。

公开(公告)号：US06455362B1

公开(公告)日：2002-09-24

申请号：US09642780

申请日：2000-08-22

申请人： Luan C. Tran ,  Mark McQueen ,  Robert Kerr

发明人： Luan C. Tran ,  Mark McQueen ,  Robert Kerr

IPC分类号： H01L21337

CPC分类号： H01L27/10894 ,  H01L27/10897 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： An integrated circuit device with improved DRAM refresh characteristics, and a novel method of making the device, is provided. A semiconductor substrate is provided with gate structures formed on its surface in each of an array portion and a peripheral portion. Single lightly doped regions are formed adjacent to the channel regions by ion implantation in the substrate. Dielectric spacers having a first width are formed on the substrate surface adjacent to the gate structures covering at least a portion of the single lightly doped regions. Heavily-doped regions are ion-implanted on opposite sides of the gate structure in the peripheral portion. The dielectric spacers are etched back to a second width smaller than the first width. Double lightly doped regions are formed by ion implantation in the substrate in an area of the substrate left exposed by the spacer etch back. Triple lightly doped regions may be also be formed by a first implant at the gate edge, a second implant through an intermediate spacer, and a third implant after the spacer etch back.

摘要翻译： 提供了具有改进的DRAM刷新特性的集成电路器件，以及制造该器件的新颖方法。 半导体基板在阵列部分和周边部分中的表面上设置有栅极结构。 单个轻掺杂区域通过在衬底中的离子注入形成在沟道区附近。 具有第一宽度的电介质间隔物形成在与覆盖单个轻掺杂区域的至少一部分的栅极结构相邻的衬底表面上。 重掺杂区域被离子注入在外围部分中的栅极结构的相对侧上。 电介质间隔物被回蚀到小于第一宽度的第二宽度。 通过离子注入形成双重轻掺杂区域，该衬底在衬底的由间隔物回蚀刻暴露的区域中。 三个轻掺杂区域也可以通过在栅极边缘处的第一注入，通过中间间隔物的第二植入物和间隔物回蚀后的第三植入物形成。

公开(公告)号：US06790663B2

公开(公告)日：2004-09-14

申请号：US10098659

申请日：2002-03-12

申请人： Robert Kerr ,  Brian Shirley ,  Luan C. Tran ,  Tyler A. Lowrey

发明人： Robert Kerr ,  Brian Shirley ,  Luan C. Tran ,  Tyler A. Lowrey

IPC分类号： H01L214763

CPC分类号： H01L27/10897 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/10891 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and related integrated circuitry constructions are described. In one embodiment, a plurality of conductive lines are formed over a substrate and diffusion regions are formed within the substrate elevationally below the lines. The individual diffusion regions are disposed proximate individual conductive line portions and collectively define therewith individual contact pads with which electrical connection is desired. Insulative material is formed over the conductive line portions and diffusion regions, with contact openings being formed therethrough to expose portions of the individual contact pads. Conductive contacts are formed within the contact openings and in electrical connection with the individual contact pads. In a preferred embodiment, the substrate and diffusion regions provide a pn junction which is configured for biasing into a reverse-biased diode configuration. In operation, the pn junction is sufficiently biased to preclude electrical shorting between the conductive line and the substrate for selected magnitudes of electrical current provided through the conductive line and the conductive material forming the conductive contacts.

摘要翻译： 描述形成触点的方法，接触线的方法，操作集成电路的方法以及相关的集成电路结构。 在一个实施例中，多个导电线形成在衬底之上，扩散区形成在衬底正下方的线下方。 单独的扩散区域设置在各个导电线部分附近，并且与其共同地限定需要电连接的各个接触焊盘。 绝缘材料形成在导电线部分和扩散区域上，其中接触开口穿过其形成以暴露各个接触焊盘的部分。 导电触点形成在接触开口内并与各个接触垫电连接。 在优选实施例中，衬底和扩散区域提供pn结，其被配置为偏置成反向偏置二极管配置。 在操作中，pn结被充分地偏置，以防止导电线和衬底之间的电短路，用于通过导电线和形成导电触点的导电材料提供的选定大小的电流。

公开(公告)号：US06580149B2

公开(公告)日：2003-06-17

申请号：US10046737

申请日：2002-01-17

申请人： Luan C. Tran ,  Mark McQueen ,  Robert Kerr

发明人： Luan C. Tran ,  Mark McQueen ,  Robert Kerr

IPC分类号： H01L2900

CPC分类号： H01L27/10894 ,  H01L27/10897 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： An integrated circuit device with improved DRAM refresh characteristics, and a novel method of making the device, is provided. A semiconductor substrate is provided with gate structures formed on its surface in each of an array portion and a peripheral portion. Single lightly doped regions are formed adjacent to the channel regions by ion implantation in the substrate. Dielectric spacers having a first width are formed on the substrate surface adjacent to the gate structures covering at least a portion of the single lightly doped regions. Heavily-doped regions are ion-implanted on opposite sides of the gate structure in the peripheral portion. The dielectric spacers are etched back to a second width smaller than the first width. Double lightly doped regions are formed by ion implantation in the substrate in an area of the substrate left exposed by the spacer etch back. Triple lightly doped regions may be also be formed by a first implant at the gate edge, a second implant through an intermediate spacer, and a third implant after the spacer etch back.

公开(公告)号：US08507341B2

公开(公告)日：2013-08-13

申请号：US13445797

申请日：2012-04-12

申请人： Luan C. Tran ,  John Lee ,  Zengtao “Tony” Liu ,  Eric Freeman ,  Russell Nielsen

发明人： Luan C. Tran ,  John Lee ,  Zengtao “Tony” Liu ,  Eric Freeman ,  Russell Nielsen

IPC分类号： H01L21/8242

CPC分类号： H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/544 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.