Method of forming ONO-type sidewall with reduced bird's beak
    1.
    发明申请
    Method of forming ONO-type sidewall with reduced bird's beak 有权
    用鸟喙形成ONO型侧壁的方法

    公开(公告)号:US20050227437A1

    公开(公告)日:2005-10-13

    申请号:US10821100

    申请日:2004-04-07

    摘要: Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the sidewall such as silicon oxide layers. As a result, a more uniform sidewall dielectric can be fabricated with more uniform breakdown voltages along it height.

    摘要翻译: 通常在ONO型存储单元堆叠周围制造侧壁氧化物通常产生鸟喙,因为在制造之前,存在ONO型存储单元堆叠的暴露的侧壁,其暴露分别由不同的多个材料层组成的多个材料层的侧面部分 材料 堆叠中的某些材料如氮化硅比堆叠中的其它材料更难以氧化,这样的多晶硅。 结果,氧化不沿着侧壁的多层高度均匀地进行。 本公开显示了基于侧壁电介质的基于基础的制造有助于减少鸟喙形成。 更具体地,表明短寿命氧化剂(例如原子氧)能够更好地氧化难以氧化的材料如氮化硅,并且表明短寿命氧化剂交替地或另外不扩散为 深深地通过侧壁的已氧化层,例如氧化硅层。 结果,可以制造更均匀的侧壁电介质,沿其高度具有更均匀的击穿电压。

    Method of forming ONO-type sidewall with reduced bird's beak
    2.
    发明授权
    Method of forming ONO-type sidewall with reduced bird's beak 有权
    用鸟喙形成ONO型侧壁的方法

    公开(公告)号:US07910429B2

    公开(公告)日:2011-03-22

    申请号:US10821100

    申请日:2004-04-07

    IPC分类号: H01L21/336

    摘要: Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the sidewall such as silicon oxide layers. As a result, a more uniform sidewall dielectric can be fabricated with more uniform breakdown voltages along it height.

    摘要翻译: 通常在ONO型存储单元堆叠周围制造侧壁氧化物通常产生鸟喙,因为在制造之前,存在ONO型存储单元堆叠的暴露的侧壁,其暴露分别由不同的多个材料层组成的多个材料层的侧面部分 材料 堆叠中的某些材料如氮化硅比堆叠中的其它材料更难以氧化,这样的多晶硅。 结果,氧化不沿着侧壁的多层高度均匀地进行。 本公开显示了基于侧壁电介质的基于基础的制造有助于减少鸟喙形成。 更具体地,表明短寿命氧化剂(例如原子氧)能够更好地氧化难以氧化的材料如氮化硅,并且表明短寿命氧化剂交替地或另外不扩散为 深深地通过侧壁的已氧化层,例如氧化硅层。 结果,可以制造更均匀的侧壁电介质,沿其高度具有更均匀的击穿电压。

    Dynamically controllable reduction of vertical contact diameter through adjustment of etch mask stack for dielectric etch
    3.
    发明申请
    Dynamically controllable reduction of vertical contact diameter through adjustment of etch mask stack for dielectric etch 有权
    通过调整用于电介质蚀刻的蚀刻掩模叠层来动态控制垂直接触直径的减小

    公开(公告)号:US20050106882A1

    公开(公告)日:2005-05-19

    申请号:US10718320

    申请日:2003-11-19

    摘要: Inwardly-tapered openings are created in an Anti-Reflection Coating layer (ARC layer) provided beneath a patterned photoresist layer. The smaller, bottom width dimensions of the inwardly-tapered openings are used for defining further openings in an interlayer dielectric region (ILD) provided beneath the ARC layer. In one embodiment, the ILD separates an active layers set of an integrated circuit from its first major interconnect layer. Further in one embodiment, a taper-inducing etch recipe is used to create the inwardly-tapered ARC openings, where the etch recipe uses a mixture of CF4 and CHF3 and where the CF4/CHF3 volumetric inflow ratio is substantially less than 5 to 1, and more preferably closer to 1 to 1.

    摘要翻译: 在设置在图案化光致抗蚀剂层下方的防反射涂层(ARC层)中产生向内锥形的开口。 向内锥形开口的较小的底部宽度尺寸用于限定在ARC层下方设置的层间介质区域(ILD)中的另外的开口。 在一个实施例中,ILD将集成电路的有源层集合与其第一主互连层分开。 此外,在一个实施例中,锥形诱导蚀刻配方用于产生向内锥形的ARC开口,其中蚀刻配方使用CF4和CHF3的混合物,其中CF4 / CHF3体积流入比基本上小于5:1, 更优选更接近1比1。

    Methods of reducing or removing micromasking residue prior to metal etch using oxide hardmask
    4.
    发明申请
    Methods of reducing or removing micromasking residue prior to metal etch using oxide hardmask 审中-公开
    使用氧化物硬掩模在金属蚀刻之前减少或去除微掩模残留物的方法

    公开(公告)号:US20050048788A1

    公开(公告)日:2005-03-03

    申请号:US10649099

    申请日:2003-08-26

    摘要: Significant amounts of micromasking residue have been observed at the interface between a Ti-containing ARC layer and a PE-TEOS hardmask after the hardmask has been etched and prior to the use of the etched hardmask for transferring a pattern to an underlying metal layer (e.g., aluminum). The micromasking residue can interfere with proper etching of the underlying metal layer such as by creating undesirable short circuits between metal interconnect lines. Methods are disclosed for removing and/or preventing the formation of the micromasking residue. A removing method includes the use of a relatively low average-mass physical bombardment agent in combination with a small-diameter, chemically-reactive agent for dislodging micromasking nodules by weakening their base anchors and breaking them away without causing excessive damage to underlying layers. In one embodiment, the base anchors are rich in titanium content while the micromasking nodule bodies contain titanium oxide. Chlorine is included in a residue removing plasma for volatizing the titanium of the base anchors while argon is further included in the residue removing plasma for physically bombarding the upper, oxide bodies of the micromasking nodules. A method for preventing or reducing the amount of formed, micromasking residue includes interposing an oxygen-poor interfacial layer between the metal-containing ARC layer and the oxygen-containing hardmask.

    摘要翻译: 在硬掩模被蚀刻之后并且在使用蚀刻的硬掩模以将图案转移到下面的金属层之前,在含Ti的ARC层和PE-TEOS硬掩模之间的界面处观察到显着量的微掩模残留物(例如 ,铝)。 微掩模残留物可能妨碍下面的金属层的适当蚀刻,例如通过在金属互连线之间产生不期望的短路。 公开了用于去除和/或防止形成微阵列残留物的方法。 除去方法包括使用相对较低的平均质量物理轰击剂与小直径的化学反应剂组合,以通过削弱其基本锚固件并将其破坏而不会对下面的层造成过度损伤来移除微拉伸结节。 在一个实施方案中,基础锚固体富含钛含量,而微组织结核体中含有氧化钛。 残留物除去等离子体中的氯,用于挥发基础锚的钛,同时氩还包括在除去等离子体的残留物中以物理地轰击微掩模结核的上部氧化物体。 防止或减少形成的微掩模残渣量的方法包括在含金属的ARC层和含氧硬掩模之间插入不透氧的界面层。

    LINE EDGE ROUGHNESS CONTROL
    5.
    发明申请
    LINE EDGE ROUGHNESS CONTROL 审中-公开
    线边缘粗糙度控制

    公开(公告)号:US20090057266A1

    公开(公告)日:2009-03-05

    申请号:US11845613

    申请日:2007-08-27

    IPC分类号: H01L21/302

    CPC分类号: H01L21/31116

    摘要: In one embodiment, a method includes providing a plasma etch reactor including a vacuum chamber and an electrode disposed inside of the chamber, and providing a stack to be etched over the electrode, the stack including a patterned photoresist over a dielectric layer. The method further includes providing a chamber pressure between about 75 mT and about 150 mT, flowing gases including CF4 and CHF3 at a ratio between about 2.5:1 and about 5.0:1 into the chamber, applying RF power to the electrode between about 300 W and about 500 W to form a plasma from the gases, and etching the dielectric layer with the plasma through the patterned photoresist.

    摘要翻译: 在一个实施例中,一种方法包括提供等离子体蚀刻反应器,该等离子体蚀刻反应器包括真空室和设置在室内部的电极,并且提供待蚀刻在电极上的叠层,所述堆叠包括介电层上的图案化光致抗蚀剂。 该方法还包括将约75mT至约150mT之间的室压力,包括大约2.5:1至大约5.0:1之间的比例的CF4和CHF3的流动气体提供到室中,在约300W之间向电极施加RF功率 和约500W,以从气体形成等离子体,并通过图案化的光致抗蚀剂用等离子体蚀刻介电层。