公开(公告)号：US12040526B2

公开(公告)日：2024-07-16

申请号：US17220151

申请日：2021-04-01

申请人： Zhuhai ACCESS Semiconductor Co., Ltd

发明人： Xianming Chen ,  Lei Feng ,  Benxia Huang ,  Jindong Feng ,  Yejie Hong

IPC分类号： H01P11/00 ,  B32B37/00 ,  C25D5/00 ,  C25D7/00 ,  B32B37/12 ,  C25D5/02

CPC分类号： H01P11/008 ,  B32B37/1284 ,  C25D5/022 ,  C25D7/00

摘要： A method for manufacturing an embedded package structure having an air resonant cavity according to an embodiment includes manufacturing a first substrate including a first insulating layer, a chip embedded in the insulating layer, and a wiring layer on a terminal face of the chip of the first substrate, wherein the wiring layer is provided thereon with an opening revealing the terminal face of the chip; manufacturing a second substrate which comprises a second insulating layer; locally applying a first adhesive layer on the wiring layer such that the opening revealing the terminal face of the chip is not covered; and applying a second adhesive layer on the second substrate; and attaching and curing the first adhesive layer of the first substrate and the second adhesive layer of the second substrate to obtain an embedded package structure having an air resonant cavity on the terminal face of the chip.

公开(公告)号：US11569177B2

公开(公告)日：2023-01-31

申请号：US16948518

申请日：2020-09-22

申请人： Zhuhai ACCESS Semiconductor Co., Ltd

发明人： Xianming Chen ,  Jindong Feng ,  Benxia Huang ,  Lei Feng ,  Jiangjiang Zhao ,  Wenshi Wang

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552

摘要： Disclosed are a method for manufacturing a support frame structure and a support frame structure. The method includes steps of: providing a metal plate including a support region and an opening region; forming an upper dielectric hole and a lower dielectric hole respectively at an upper surface and a lower surface of the support region by photolithography, with a metal spacer connected between the upper dielectric hole and the lower dielectric hole; forming an upper metal pillar on an upper surface of the metal plate, and laminating an upper dielectric layer which covers the upper metal pillar and the upper dielectric hole; etching the metal spacer, forming a lower metal pillar on the lower surface of the metal plate, and laminating a lower dielectric layer which covers the lower metal pillar and the lower dielectric hole.

公开(公告)号：US12002734B2

公开(公告)日：2024-06-04

申请号：US17411144

申请日：2021-08-25

申请人： Zhuhai ACCESS Semiconductor Co., Ltd

发明人： Xianming Chen ,  Lei Feng ,  Benxia Huang ,  Jindong Feng ,  Minxiong Li ,  Shigui Xin ,  Wenshi Wang

IPC分类号： H01L23/40 ,  H01L23/373

CPC分类号： H01L23/40 ,  H01L23/3736

摘要： A circuit prearranged heat dissipation embedded packaging structure according to an embodiment of the present disclosure includes at least one chip and a support frame surrounding the at least one chip. The support frame may include a via pillar passing through the support frame in the height direction, a first wiring layer on a first surface of the support frame, and a heat dissipation layer on the back face of the chip. The first wiring layer is flush with or higher than the first surface, the first wiring layer is in conductive connection with the heat dissipation layer, a gap between the chip and the frame is completely filled with the dielectric material, a second wiring layer is formed on a terminal face of the chip, and the second wiring layer is in conductive connection with the first wiring layer through the via pillar.

公开(公告)号：US11854920B2

公开(公告)日：2023-12-26

申请号：US17044087

申请日：2020-05-12

申请人： Zhuhai ACCESS Semiconductor Co., Ltd.

发明人： Xianming Chen ,  Jindong Feng ,  Benxia Huang ,  Lei Feng ,  Wenshi Wang

IPC分类号： H01L23/31 ,  H01L23/04 ,  H01L23/29 ,  H01L23/36 ,  H01L23/48 ,  H01L23/485 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L23/3107 ,  H01L21/561 ,  H01L21/568 ,  H01L23/041 ,  H01L23/293 ,  H01L23/36 ,  H01L23/481 ,  H01L23/485 ,  H01L24/96

摘要： An embedded chip package according to an embodiment of the present application may include at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip.