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Patent Agency Ranking
公开(公告)号：US11973507B2
公开(公告)日：2024-04-30
申请号：US17924747
申请日：2021-04-13
Applicant: ams International AG
Inventor： Vincenzo Leonardo
Abstract: A comparator circuit includes an input stage with a set of differential current paths and a pair of differential input transistors connected to a pair of input terminals. An output stage includes an output current path between a first and a second supply terminal, an output transistor connected in the output current path and having a control terminal coupled to the set of differential current paths, and a comparator output connected to the output current path. An auxiliary stage includes an auxiliary current path between the supply terminals, an auxiliary current source, a first auxiliary transistor connected in the auxiliary current path and having a control terminal connected to the control terminal of the output transistor, and a voltage follower with a second auxiliary transistor and a third auxiliary transistor. The second auxiliary transistor controls the voltage follower and the third auxiliary transistor couples the control terminal of the output transistor to at least one of the set of differential current paths.
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公开(公告)号：US11165396B2
公开(公告)日：2021-11-02
申请号：US16617107
申请日：2018-05-25
Applicant: ams International AG
Inventor： Srinidhi Koushik Kanagal Ramesh , Vincenzo Leonardo
Abstract: An amplifier arrangement comprises a sensor input and a first and a second amplifier. The first amplifier has a first amplifier output and a first input connected to a first reference potential terminal and a second input connected to the sensor input in a direct fashion and to the first amplifier output via a feedback path having a switched integration capacitor that is charged by the feedback path during a first switching phase and discharged during a second switching phase. The second amplifier has a second amplifier output, a first input connected to a second reference potential terminal and a second input. A first feedback capacitor is connected in-between two pairs of feedback switches. A second feedback capacitor is connected between the second amplifier output and the second input of the second amplifier. An impedance element is coupled between the second amplifier output and the sensor input.
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公开(公告)号：US20200186105A1
公开(公告)日：2020-06-11
申请号：US16617107
申请日：2018-05-25
Applicant: ams International AG
Inventor： Srinidhi Koushik KANAGAL RAMESH , Vincenzo Leonardo
Abstract: An amplifier arrangement comprises a sensor input and a first and a second amplifier. The first amplifier has a first amplifier output and a first input connected to a first reference potential terminal and a second input connected to the sensor input in a direct fashion and to the first amplifier output via a feedback path having a switched integration capacitor that is charged by the feedback path during a first switching phase and discharged during a second switching phase. The second amplifier has a second amplifier output, a first input connected to a second reference potential terminal and a second input. A first feedback capacitor is connected in-between two pairs of feedback switches. A second feedback capacitor is connected between the second amplifier output and the second input of the second amplifier. An impedance element is coupled between the second amplifier output and the sensor input.
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公开(公告)号：US12047056B2
公开(公告)日：2024-07-23
申请号：US18000950
申请日：2021-06-09
Applicant: ams International AG
Inventor： Camillo Stefanucci , Vincenzo Leonardo
IPC: H03K17/042 , H03K17/0812 , H03K17/687
CPC classification number: H03K17/04206 , H03K17/08122 , H03K17/6871
Abstract: A circuit arrangement is provided where the arrangement of a feedback resistor between a first branch and a second branch enables that a voltage is provided at an output terminal in an efficient way, this means with a high settling speed and a low current consumption. The feedback resistor is arranged between a reference node and the output terminal, where the reference node is connected to a current mirror. The circuit arrangement can be employed as a gate driver. Furthermore, a driver block and a method of driving a circuit arrangement are provided.
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公开(公告)号：US11838012B2
公开(公告)日：2023-12-05
申请号：US17921432
申请日：2021-04-19
Applicant: ams International AG
Inventor： Vincenzo Leonardo
CPC classification number: H03K17/145 , G05F1/56 , G05F3/30 , H03K17/22
Abstract: A power on reset circuit comprises terminals for reference and supply potentials and a voltage divider coupled therebetween. First and second transistors of a bandgap circuit are resistively coupled to the reference potential terminal and have bases connected to the voltage divider. Current mirrors couple the collectors of the first and second transistors to an output terminal providing an output signal indicating a power on reset condition. A first compensation transistor is coupled between the collector of one of the transistors and the reference potential terminal, and a second compensation transistor is coupled between the output terminal and the reference potential terminal to compensate the effect of parasitic substrate currents in response to an external interference.
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