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Patent Agency Ranking
公开(公告)号：US20160335101A1
公开(公告)日：2016-11-17
申请号：US15151746
申请日：2016-05-11
Inventor： Jochen SAUER , Robert LEINFELLNER , Matthias KLEMM , Thorsten BREHM , Robert POLNAU , Matthias SCHMITZ
CPC classification number: G06F13/102 , G06F9/4411 , G06F9/44505 , G06F13/126 , G06F13/20 , G06F13/385 , G06F13/4022 , G06F13/4068 , G06F13/4072 , G06F15/7885 , G11C8/18
Abstract: A method for configuring an interface unit of a computer system with a first processor and a second processor stored in the interface unit. A data link is set up between the first processor and the second processor. A peripheral of the computer system is configured to store input data in an input data channel and to read output data from an output data channel, and the second processor is configured to read the input data from the input data channel and to store output data in the output data channel. A sequence of processor commands for the second processor is created such that a number of subsequences is created.
Abstract translation: 一种用于配置具有存储在接口单元中的第一处理器和第二处理器的计算机系统的接口单元的方法。 在第一处理器和第二处理器之间建立数据链路。 计算机系统的外围设备被配置为将输入数据存储在输入数据通道中并从输出数据通道读取输出数据，并且第二处理器被配置为从输入数据通道读取输入数据并将输出数据存储在 输出数据通道。 创建用于第二处理器的处理器命令的序列，使得创建多个子序列。
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公开(公告)号：US20190165996A1
公开(公告)日：2019-05-30
申请号：US15822521
申请日：2017-11-27
Inventor： Matthias KLEMM , Heiko KALTE , Robert POLNAU , Thorsten BREHM , Jochen SAUER , Hans-Juergen MIKS , Robert LEINFELLNER , Ruediger KRAFT , Magnus ASPLUND , Matthias SCHMITZ
Abstract: A method for operating a real-time-capable simulation network having multiple network nodes for computing a simulation model. The network nodes are connected to one another via a serial data bus, and the network nodes exchange data via data bus messages. At least one event-driven task of the simulation model is implemented on a first network node, and a nondeterministic triggering event is detected by a second network node. The second network node communicates the detected triggering event to the first network node and the first network node computes the event-driven task. A fast response time is achieved by the means that a detection signal is sent from the second network node in the form of a multicast data bus message or a broadcast data bus message to multiple network nodes of the simulation network or to all network nodes of the simulation network over the serial data bus.
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公开(公告)号：US20160335203A1
公开(公告)日：2016-11-17
申请号：US15151767
申请日：2016-05-11
Inventor： Jochen SAUER , Robert LEINFELLNER , Matthias KLEMM , Thorsten BREHM , Robert POLNAU , Matthias SCHMITZ
CPC classification number: G06F13/102 , G06F9/4411 , G06F9/44505 , G06F13/126 , G06F13/20 , G06F13/385 , G06F13/4022 , G06F13/4068 , G06F13/4072 , G06F15/7885 , G11C8/18
Abstract: An interface unit for data exchange between a first processor of a computer system and a peripheral environment. The interface unit has a number of input data channels for receiving input data from the peripheral environment and a first access management unit. The access management unit is configured to receive a request for providing the input data, stored in the number of input data channels, from a first interface processor stored in the interface unit and from a second interface processor stored in the interface unit and to provide or not to provide the input data, stored in the number of input data channels, to the first interface processor and the second interface processor. A first priority and a second priority can be stored in the first access management unit.
Abstract translation: 一种用于在计算机系统的第一处理器和外围环境之间进行数据交换的接口单元。 接口单元具有用于从外围环境接收输入数据的多个输入数据通道和第一访问管理单元。 访问管理单元被配置为从存储在接口单元中的第一接口处理器和存储在接口单元中的第二接口处理器接收提供存储在输入数据通道数量中的输入数据的请求，并且提供或 不将存储在输入数据通道中的输入数据提供给第一接口处理器和第二接口处理器。 第一优先级和第二优先级可以存储在第一访问管理单元中。
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公开(公告)号：US20190146035A1
公开(公告)日：2019-05-16
申请号：US16229696
申请日：2018-12-21
Inventor： Matthias KLEMM , Daniel BALDIN
IPC: G01R31/3185 , G05B23/02 , G01R31/319
Abstract: A method is disclosed for synchronizing a checking apparatus, in which the checking apparatus is configured for testing at least one first electronic closed-loop control unit. Further disclosed is a checking apparatus which is transferable to a synchronized state. Additionally disclosed is a composite system which includes at least two checking apparatuses. Also disclosed are a checking apparatus for testing at least one first closed-loop control unit, and a composite system including at least one checking apparatus and a further checking apparatus, the latter checking apparatus being configured to have the same effect as the first checking apparatus.
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公开(公告)号：US20190107577A1
公开(公告)日：2019-04-11
申请号：US16205765
申请日：2018-11-30
Inventor： Matthias KLEMM
IPC: G01R31/317
Abstract: A checking apparatus can test at least one first closed-loop control unit. The checking apparatus can include a first timing transmission unit which can generate a first periodic timing signal from a first time signal, and which can output the first periodic timing signal to a first PLL. The check device can further include a first oscillator which can generate a second periodic timing signal and which can output the second periodic timing signal to a second PLL. The checking device can additionally include a first clock, and can forward a first clock signal to a first input/output unit, and/or to a first computation unit. A first changeover signal can be used to control a first multiplexer such that depending on a state of the first changeover signal, the first multiplexer can forward either a first frequency-stabilized timing signal or a second frequency-stabilized timing signal to the first clock.
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