公开(公告)号：US20210344338A1

公开(公告)日：2021-11-04

申请号：US17325867

申请日：2021-05-20

Applicant: pSemi Corporation

Inventor： Simon Edward Willard ,  Tero Tapio Ranta ,  Matt Allison ,  Shashi Ketan Samal

IPC: H03K17/10 ,  H03K17/0412 ,  H03K17/687 ,  H01L27/07 ,  H01L27/12 ,  H01L25/065 ,  H03K17/693 ,  H03K17/06 ,  H03K17/16

Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

公开(公告)号：US20250150073A1

公开(公告)日：2025-05-08

申请号：US19017326

申请日：2025-01-10

Applicant: pSemi Corporation

Inventor： Simon Edward Willard ,  Tero Tapio Ranta ,  Matt Allison ,  Shashi Ketan Samal

IPC: H03K17/10 ,  H01L25/065 ,  H03K17/0412 ,  H03K17/06 ,  H03K17/16 ,  H03K17/687 ,  H03K17/693 ,  H10D84/80 ,  H10D86/00

Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

公开(公告)号：US12237327B2

公开(公告)日：2025-02-25

申请号：US17523816

申请日：2021-11-10

Applicant: pSemi Corporation

Inventor： Shashi Samal ,  Matt Allison

IPC: H01L27/085 ,  H01L21/822 ,  H01L27/02

Abstract: Devices and methods to manufacture a stack of FET switches in presence of a neighboring stack of FET switches are described. The stack of FET switches is designed or manufactured so that at least its top FET has a width that is smaller than the width of its bottom FET. Other voltage handling configurations and distributions of widths are described.

公开(公告)号：US10523195B1

公开(公告)日：2019-12-31

申请号：US16053710

申请日：2018-08-02

Applicant: pSemi Corporation

Inventor： Yuan Luo ,  Matt Allison ,  Eric S. Shapiro

IPC: H03K17/16

Abstract: Embodiments include a switch stack comprising ACS FETs and mixed-style gate resistor bias networks that mitigate the effects of high leakage current. By carefully selecting the number of ACS FETs in a sub-stack that uses a rung gate resistor bias network versus a sub-stack that uses a rail gate resistor bias network, as well as by selecting particularly useful values for the gate resistors in each bias network, a tradeoff can be achieved between adverse Vg offset and Q factor. The switch stack may be configured with rung-rail gate resistor bias networks, or with rung-rail-rung gate resistor bias networks. Other embodiments include mixed-style body resistor bias networks in switch stacks comprising non-ACS FETs. Some embodiments include one or more positive-logic FETs M1-Mn, series-coupled on at least one end to an “end-cap” FET M0 of a type that turns OFF when the applied VGS is essentially zero volts.

公开(公告)号：US11418183B2

公开(公告)日：2022-08-16

申请号：US17325867

申请日：2021-05-20

Applicant: pSemi Corporation

Inventor： Simon Edward Willard ,  Tero Tapio Ranta ,  Matt Allison ,  Shashi Ketan Samal

IPC: H03K17/16 ,  H04B1/44 ,  H03K17/10 ,  H03K17/0412 ,  H03K17/687 ,  H01L27/07 ,  H01L27/12 ,  H01L25/065 ,  H03K17/693 ,  H03K17/06

Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

公开(公告)号：US10886911B2

公开(公告)日：2021-01-05

申请号：US15939132

申请日：2018-03-28

Applicant: pSemi Corporation

Inventor： Simon Edward Willard ,  Tero Tapio Ranta ,  Matt Allison ,  Shashi Ketan Samal

IPC: H03K17/687 ,  H03K17/10 ,  H01L25/065 ,  H03K17/0412 ,  H01L27/12 ,  H03K17/693 ,  H01L27/07

Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

公开(公告)号：US12081210B2

公开(公告)日：2024-09-03

申请号：US18473742

申请日：2023-09-25

Applicant: pSemi Corporation

Inventor： Eric S. Shapiro ,  Ravindranath D. Shrivastava ,  Fleming Lam ,  Matt Allison

IPC: H03K17/687

CPC classification number: H03K17/6871

Abstract: A FET switch stack and a method to operate a FET switch stack. The FET switch stack includes a stacked arrangement of body bypass FET switches connected across respective common body resistors. The body bypass FET switches bypass the respective common body resistors during the OFF steady state of the FET switch stack and do not bypass the respective common body resistors during the ON steady state.

公开(公告)号：US20240063785A1

公开(公告)日：2024-02-22

申请号：US18466601

申请日：2023-09-13

Applicant: pSemi Corporation

Inventor： Simon Edward Willard ,  Tero Tapio Ranta ,  Matt Allison ,  Shashi Ketan Samal

IPC: H03K17/10 ,  H01L25/065 ,  H01L27/07 ,  H01L27/12 ,  H03K17/0412 ,  H03K17/06 ,  H03K17/16 ,  H03K17/687 ,  H03K17/693

CPC classification number: H03K17/102 ,  H01L25/0657 ,  H01L27/0727 ,  H01L27/1203 ,  H03K17/0412 ,  H03K17/063 ,  H03K17/162 ,  H03K17/6871 ,  H03K17/6872 ,  H03K17/6874 ,  H03K17/693 ,  H03K2017/066 ,  H03K2217/0009 ,  H03K2217/0054

Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

公开(公告)号：US20190305768A1

公开(公告)日：2019-10-03

申请号：US15939132

申请日：2018-03-28

Applicant: pSemi Corporation

Inventor： Simon Edward Willard ,  Tero Tapio Ranta ,  Matt Allison ,  Shashi Ketan Samal

IPC: H03K17/10 ,  H01L25/065 ,  H03K17/0412 ,  H01L27/12 ,  H03K17/687 ,  H03K17/693 ,  H01L27/07

Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

公开(公告)号：US10256287B2

公开(公告)日：2019-04-09

申请号：US15910939

申请日：2018-03-02

Applicant: pSemi Corporation

Inventor： Eric S. Shapiro ,  Matt Allison

IPC: H01L49/02 ,  H01L29/78 ,  H01L27/02 ,  H03K17/16 ,  H03K17/0412 ,  H01L27/06 ,  H01L27/12

Abstract: Embodiments of systems, methods, and apparatus for improving ESD performance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates.