公开(公告)号：US10432238B1

公开(公告)日：2019-10-01

申请号：US16005589

申请日：2018-06-11

Applicant: pSemi Corporation

Inventor： Chengkai Luo ,  Fleming Lam

IPC: H04B1/00 ,  H04B1/44 ,  H04B15/00 ,  H03F1/56 ,  H03F3/193 ,  H03F3/21

Abstract: Detuning and isolation techniques for a multiband tunable matching network used in multi-transceiver RF systems. Embodiments include an amplifier and a multiband tunable matching network (MN) coupled to the amplifier. The multiband tunable MN is configured to detune to an isolation OFF state from an ON state, wherein the match tuning in the isolation OFF state is different than match tuning in the ON state. In an example detuning, the match tuning in the isolation OFF state is in a different frequency band than a frequency band of match tuning in the ON state and is selected based on the frequency band of match tuning in the ON state.

公开(公告)号：US10003322B2

公开(公告)日：2018-06-19

申请号：US15287335

申请日：2016-10-06

Applicant: pSemi Corporation

Inventor： Fleming Lam

IPC: H01P1/22 ,  H03H11/24 ,  H03H7/24 ,  H03H7/25

CPC classification number: H03H11/245 ,  H01P1/22 ,  H03H7/24 ,  H03H7/251

Abstract: Circuits and methods for eliminating or mitigating the amount of temperature-dependent variation in the relative attenuation of a multi-valued digital step attenuator (DSA) by using resistive components having temperature-dependent resistance values that compensate for or offset changes in the temperature-dependent ON resistance (RON) of the switches within the DSA. In some embodiments, DSA attenuator cell switches are fabricated to have positive first-order resistance temperature (FORT) coefficients, while temperature-compensating series attenuation resistances are fabricated as a positive FORT coefficient resistor and temperature-compensating shunt resistances are fabricated as either a negative FORT coefficient resistor or a combination of a negative FORT coefficient resistor in parallel with a positive FORT coefficient resistor.

公开(公告)号：US12081210B2

公开(公告)日：2024-09-03

申请号：US18473742

申请日：2023-09-25

Applicant: pSemi Corporation

Inventor： Eric S. Shapiro ,  Ravindranath D. Shrivastava ,  Fleming Lam ,  Matt Allison

IPC: H03K17/687

CPC classification number: H03K17/6871

Abstract: A FET switch stack and a method to operate a FET switch stack. The FET switch stack includes a stacked arrangement of body bypass FET switches connected across respective common body resistors. The body bypass FET switches bypass the respective common body resistors during the OFF steady state of the FET switch stack and do not bypass the respective common body resistors during the ON steady state.

公开(公告)号：US11671135B2

公开(公告)日：2023-06-06

申请号：US17492199

申请日：2021-10-01

Applicant: pSemi Corporation

Inventor： Ravindranath D. Shrivastava ,  Fleming Lam ,  Payman Shanjani

IPC: H04B1/40 ,  H03F3/24 ,  H03H11/28

CPC classification number: H04B1/40 ,  H03F3/245 ,  H03H11/28 ,  H03F2200/294 ,  H03F2200/451

Abstract: An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.

公开(公告)号：US10277201B2

公开(公告)日：2019-04-30

申请号：US15981722

申请日：2018-05-16

Applicant: pSemi Corporation

Inventor： Fleming Lam

IPC: H03H11/24 ,  H03H7/24 ,  H01P1/22 ,  H03H7/25

Abstract: Circuits and methods for eliminating or mitigating the amount of temperature-dependent variation in the relative attenuation of a multi-valued digital step attenuator (DSA) by using resistive components having temperature-dependent resistance values that compensate for or offset changes in the temperature-dependent ON resistance (RON) of the switches within the DSA. In some embodiments, DSA attenuator cell switches are fabricated to have positive first-order resistance temperature (FORT) coefficients, while temperature-compensating series attenuation resistances are fabricated as a positive FORT coefficient resistor and temperature-compensating shunt resistances are fabricated as either a negative FORT coefficient resistor or a combination of a negative FORT coefficient resistor in parallel with a positive FORT coefficient resistor.

公开(公告)号：US20180262181A1

公开(公告)日：2018-09-13

申请号：US15981722

申请日：2018-05-16

Applicant: pSemi Corporation

Inventor： Fleming Lam

IPC: H03H11/24 ,  H03H7/25 ,  H03H7/24 ,  H01P1/22

CPC classification number: H03H11/245 ,  H01P1/22 ,  H03H7/24 ,  H03H7/251

Abstract: Circuits and methods for eliminating or mitigating the amount of temperature-dependent variation in the relative attenuation of a multi-valued digital step attenuator (DSA) by using resistive components having temperature-dependent resistance values that compensate for or offset changes in the temperature-dependent ON resistance (RON) of the switches within the DSA. In some embodiments, DSA attenuator cell switches are fabricated to have positive first-order resistance temperature (FORT) coefficients, while temperature-compensating series attenuation resistances are fabricated as a positive FORT coefficient resistor and temperature-compensating shunt resistances are fabricated as either a negative FORT coefficient resistor or a combination of a negative FORT coefficient resistor in parallel with a positive FORT coefficient resistor.

公开(公告)号：US12101072B2

公开(公告)日：2024-09-24

申请号：US17933230

申请日：2022-09-19

Applicant: pSemi Corporation

Inventor： Ravindranath D. Shrivastava ,  Fleming Lam ,  Payman Shanjani

IPC: H03H11/24 ,  H03H7/20

CPC classification number: H03H11/245 ,  H03H7/20

Abstract: Methods and devices to reduce glitches in phase shifters implementing high isolation switches are disclosed. Such glitches occur at the output of the phase shifters when transitioning from one phase shift to another. The disclosed method implements delays in various steps of the phase shifter transitions. Exemplary embodiments implementing single-pole multi-throw are provided and exemplary performance of the disclosed methods are also presented. The described methods are also applicable to multi-step attenuators.