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1.发明授权公开(公告)号：US12056068B2
公开(公告)日：2024-08-06
申请号：US17867638
申请日：2022-07-18
发明人： Paul Hill
CPC分类号： G06F13/1673 , G06F13/1689 , G06F13/24 , G06F13/4072 , G06F13/4282
摘要： A memory device A memory device can include a serial interface (IF) configured to receive an operational code (op code) of no less than 16-bits and provide a plurality of acknowledgement values in response to the received op code. Controller circuits can generate the plurality of acknowledgement values, including first and second acknowledgement values in response to an operation indicated by the op code being completed, and first and third acknowledgement values in response to an operation indicated by the op code not being completed. Memory circuits can be configured to execute the operation indicated by the op code to access the nonvolatile memory cells, and indicate to the controller circuits whether or not the operation was completed. The first, second and third acknowledgement values can be different multi-bit values. Corresponding methods and systems are also disclosed.
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公开(公告)号：US20220156345A1
公开(公告)日：2022-05-19
申请号：US17601778
申请日：2020-05-28
发明人： John R. Jameson
摘要： A memory device includes a memory array arranged in rows and columns; memory cell layers at each row and column intersection, where each memory cell layer is configured to be set to a predetermined conductance state; a row control circuit that is configured to apply voltages to the rows by applying sub-voltages on each row, where each sub-voltage corresponds to a different memory cell layer, and where each sub-voltage is proportional to the voltage on the corresponding row; and a sensing circuit that is configured to determine a column current flowing through a selected column in response to the application of the voltages to the rows, where the column current is a sum of currents through each memory cell layer that corresponds to the selected column.
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公开(公告)号：US10984861B1
公开(公告)日：2021-04-20
申请号：US16032012
申请日：2018-07-10
发明人： Ishai Naveh , Venkatesh P. Gopinath , John Dinh , Mark T. Ramsbey
IPC分类号： G11C13/00
摘要： A memory device can include a plurality of memory cells formed in a substrate, each having a resistive element programmable between at least two different resistance states, including memory cells configured to store data received by the memory device, and reference cells; a reference circuit formed in the substrate configured to generate at least a first reference resistance from resistances of a plurality of reference cells; a sense circuit formed in the substrate coupled to the memory cells and at least the first reference resistance and configured to compare a resistance of a selected memory cell to at least the first reference resistance to determine the data stored by the selected memory cell.
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公开(公告)号：US10777268B2
公开(公告)日：2020-09-15
申请号：US16188224
申请日：2018-11-12
IPC分类号： G11C13/00 , G11C11/412 , G11C14/00
摘要： An integrated circuit (IC) device can include static random access memory (SRAM) cells that each include a pair of latching devices, and first and second resistive elements disposed over the latching devices. The first resistive element can be conductively connected to a first data latching node by a first vertical connection. The second resistive element can be conductively connected to a second data latching node by a second vertical connection. Each resistive element can include at least one memory layer that is capable of being programmed between at least a high and lower resistance state by application of electric fields, the resistive elements having only the high resistance state.
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公开(公告)号：US10521154B2
公开(公告)日：2019-12-31
申请号：US15743330
申请日：2016-08-16
发明人： Bard M. Pedersen
摘要： A method of controlling an ultra-deep power down (UDPD) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-UDPD (AUDPD) configuration bit from a status register; switching the interface to a Single SPI mode in response to the write command and the AUDPD configuration bit being set; completing the write operation on the memory device; automatically entering the UDPD mode upon completion of the write operation in response to the AUDPD configuration bit being set; and entering a standby mode upon completion of the write operation in response to the AUDPD configuration bit being cleared.
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公开(公告)号：US10509589B2
公开(公告)日：2019-12-17
申请号：US15329485
申请日：2015-08-13
发明人： Gideon Intrater , Bard Pedersen
IPC分类号： G06F12/00 , G06F3/06 , G06F12/0868
摘要： A method of controlling a memory device can include: (i) receiving a first read command for a critical byte, where the critical byte resides in a first group of a memory array on the memory device; (ii) reading the critical byte from the memory array in response to the first read command, and providing the critical byte; (iii) reading a next byte in the first group; (iv) outputting the next byte from the first group when a clock pulse; (v) repeating the reading the next byte and the outputting the next byte for each byte in the first group; (vi) reading a first byte in a second group of the memory array, where the second group is sequential to the first group, and where each group is allocated to a cache line; and (vii) outputting the first byte from the second group when a clock pulse is received.
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公开(公告)号：US10181496B1
公开(公告)日：2019-01-15
申请号：US15143310
申请日：2016-04-29
IPC分类号： H01L29/786 , H01L27/24 , H01L45/00 , G11C13/00
摘要： A memory device can include at least one plate structure formed over a semiconductor substrate; an active region formed within the semiconductor substrate without lateral isolation structures; a plurality of bit line contact groups, each including bit line contacts to the active region disposed in a first direction; a plurality of storage contact groups, each including storage contacts to the active region disposed in the first direction; a plurality of gate structures, each including a main section extending in the first direction, and disposed between one bit line contact group and an adjacent storage contact group; and a two-terminal storage element disposed between each bit line contact and the at least one plate structure.
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公开(公告)号：US10031869B1
公开(公告)日：2018-07-24
申请号：US14665831
申请日：2015-03-23
发明人： Gideon Intrater , Bard Pedersen , Paul Hill
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F13/16 , G06F12/122 , G11C11/406 , G11C7/10 , G06F12/0831 , G06F12/0802 , G06F12/0868
摘要： In one embodiment, a cached memory device can include: (i) a memory array coupled to a system address bus and an internal data bus; (ii) a plurality of data buffers coupled to a system data bus, and to the memory array via the internal data bus; (iii) a plurality of valid bits, where each valid bit corresponds to one of the data buffers; (iv) a plurality of buffer address registers coupled to the system address bus, where each buffer address register corresponds to one of the data buffers; and (v) a plurality of compare circuits coupled to the system address bus, where each compare circuit corresponds to one of the data buffers.
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9.发明授权Dual program state cycling algorithms for resistive switching memory device 有权用于电阻式开关存储器件的双程序状态循环算法公开(公告)号：US09524777B1
公开(公告)日：2016-12-20
申请号：US15071567
申请日：2016-03-16
CPC分类号： G11C13/0097 , G11C11/5614 , G11C11/5685 , G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C2213/79
摘要： A method of controlling a resistive switching memory cell can include: receiving a first command to be executed on the resistive switching memory cell; performing, in response to the first command, an erase operation to erase the resistive switching memory cell to an erased state; verifying the erased state of the resistive switching memory cell; performing a weak program operation to program the resistive switching memory cell to a first programmed state; and verifying the first programmed state of the resistive switching memory cell.
摘要翻译： 控制电阻式开关存储单元的方法可以包括：接收要在电阻式开关存储单元上执行的第一命令; 响应于所述第一命令执行擦除操作以将所述电阻式开关存储器单元擦除为擦除状态; 验证电阻式开关存储单元的擦除状态; 执行弱编程操作以将所述电阻式开关存储器单元编程为第一编程状态; 以及验证电阻式开关存储单元的第一编程状态。
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10.发明授权System architectures with data transfer paths between different memory types 有权具有不同存储器类型之间的数据传输路径的系统架构公开(公告)号：US09455036B1
公开(公告)日：2016-09-27
申请号：US14868363
申请日：2015-09-28
发明人： Ed McKernan , Malcolm Wing , Ravi Sunkavalli
IPC分类号： G11C11/34 , G11C14/00 , G11C13/00 , G11C11/408
CPC分类号： G11C14/0045 , G11C11/005 , G11C11/401 , G11C11/408 , G11C11/409 , G11C11/4096 , G11C13/0011 , G11C13/0023 , G11C13/0069 , G11C14/00
摘要： A system can include a first memory section comprising a plurality of volatile memory cells; a second memory section comprising a plurality of nonvolatile memory cells; a first data path configured to transfer data between the first and second memory sections; an interface circuit coupled to receive access commands and address values, the interface circuit configured to determine if a data transfer operation is occurring in the device, and if the data transfer operation is occurring, accessing the address in the first memory section or accessing a location in the second memory section based on a select value, and if the data transfer operation is not occurring, accessing the address in the first memory section; and a compare circuit configured to compare a received address to a predetermined value to generate the select value.
摘要翻译： 系统可以包括包括多个易失性存储器单元的第一存储器部分; 第二存储器部分，包括多个非易失性存储器单元; 第一数据路径，被配置为在所述第一和第二存储器部分之间传送数据; 接口电路，其被接收以接收访问命令和地址值，所述接口电路被配置为确定所述设备中是否正在发生数据传送操作，并且如果所述数据传送操作正在发生，则访问所述第一存储器部分中的地址或访问位置 在第二存储器部分中基于选择值，并且如果没有发生数据传送操作，则访问第一存储器部分中的地址; 以及比较电路，被配置为将接收到的地址与预定值进行比较以生成所述选择值。
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