公开(公告)号：US11119967B1

公开(公告)日：2021-09-14

申请号：US15083041

申请日：2016-03-28

申请人： Aquantia Corporation

发明人： Paul Langner

IPC分类号： G06F13/42 ,  G06F13/16

摘要： A system including an Ethernet transceiver PHY and a network device is disclosed. The Ethernet transceiver PHY includes register circuitry to store information associated with operating characteristics of the PHY. The network device couples to the Ethernet transceiver PHY in a closed system architecture and includes a system processor and an MDIO interface. The MDIO interface interacts with the PHY register circuitry during a normal operating mode. The system includes system interface circuitry to receive requests for accessing the register circuitry in a debug operating mode. The requests are generated external to the closed system architecture.

公开(公告)号：US10892880B1

公开(公告)日：2021-01-12

申请号：US15228161

申请日：2016-08-04

申请人： Aquantia Corporation

发明人： Kamal Dalmia

IPC分类号： H04L5/14 ,  G06F1/3203 ,  H04B1/40 ,  H04L12/40

摘要： In present embodiments, operation methods and apparatus for reducing power consumption in a 10GBASE-T transceiver circuit having transmit circuitry and receive circuitry for coupling to a plurality of physical channels are provided to transmit first data with the transmit circuitry in a first direction, receive second data with the receive circuitry in a second direction opposite to the first direction, identify an end-of-data indicator associated with the second data, and deactivate the receive circuitry in response to the end-of-data indicator. Preferably, in some embodiments, the receive circuitry is selectively switched off to reduce power consumption.

公开(公告)号：US08861663B1

公开(公告)日：2014-10-14

申请号：US13350624

申请日：2012-01-13

申请人： Hossein Sedarat ,  Fadi Saibi

发明人： Hossein Sedarat ,  Fadi Saibi

IPC分类号： H04B1/10

CPC分类号： H04L25/03012 ,  H04L2025/03426

摘要： A method of operation in an ethernet receiver circuit is disclosed. The method comprises sampling an input signal to generate a sampled signal having a sampled noise component and a sampled data component. The sampled signal is sliced, and a slicer error determined based on the slicing of the sampled signal. A subsequently sampled noise component is filtered based on the slicer error.

摘要翻译： 公开了以太网接收机电路中的操作方法。 该方法包括对输入信号进行采样以产生具有采样噪声分量和采样数据分量的采样信号。 采样信号被分片，并且基于采样信号的分片确定限幅器误差。 基于限幅器误差对随后采样的噪声分量进行滤波。

公开(公告)号：US08804582B1

公开(公告)日：2014-08-12

申请号：US13974551

申请日：2013-08-23

申请人： Aquantia Corporation

发明人： Dimitry Taich ,  Jose Tellado

IPC分类号： H04B1/44

CPC分类号： H04L12/10

摘要： An apparatuses and methods of setting power back-off of a master transceiver and a slave transceiver is disclosed. One example of a method includes the master transceiver determining a master power back-off, and the slave transceiver determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off. One example of an apparatus includes a master transceiver and slave transceiver system. The slave transceiver is connected to the master transceiver through a cable. The master transceiver includes means for determining a master power back-off. The slave transceiver includes means for determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off.

摘要翻译： 公开了一种设置主收发器和从属收发器的功率回退的装置和方法。 方法的一个示例包括主收发器确定主功率回退，并且从收发器基于从主收发器接收的信号以及基于主功率回退确定从功率回退。 设备的一个示例包括主收发器和从收发器系统。 从设备收发器通过电缆连接到主收发器。 主收发器包括用于确定主功率回退的装置。 从属收发器包括用于基于从主收发器接收的信号以及基于主功率回退确定从功率回退的装置。

公开(公告)号：US08284007B1

公开(公告)日：2012-10-09

申请号：US12604343

申请日：2009-10-22

申请人： Paul Langner ,  Ramin Farjadrad ,  Ramin Shirani ,  Jerry A. Martinson ,  Thomas Wayne Gandy

发明人： Paul Langner ,  Ramin Farjadrad ,  Ramin Shirani ,  Jerry A. Martinson ,  Thomas Wayne Gandy

IPC分类号： H01F21/02 ,  H01F27/28 ,  H04M9/08 ,  H04B3/28 ,  H04B3/00 ,  H04B1/00 ,  H03H7/00 ,  G01R15/18 ,  G01R19/22

CPC分类号： H04B3/32 ,  H01F19/04 ,  H04B3/30 ,  H04L25/0276 ,  H04L27/2647

摘要： A magnetic package for a communication system is disclosed the package comprises a plurality of transformers, wherein each transformer comprises a differential transformer. Each differential transformer comprises at least 2 sets of three pins. Each transformer is coupled to a twisted pair channel and a transceiver. The magnetic package includes at least one common mode transformer coupled to at least one of the transformers, wherein the at least one common mode transformer includes at least three pins. The at least three pins for the at least one common mode transformer are in a position relative to the other pins such that the package size is minimized.

摘要翻译： 公开了一种用于通信系统的磁性封装，该封装包括多个变压器，其中每个变压器包括差动变压器。 每个差分变压器包括至少2组三个引脚。 每个变压器耦合到双绞线通道和收发器。 磁性封装包括耦合到至少一个变压器的至少一个共模变压器，其中至少一个共模变压器包括至少三个引脚。 用于至少一个共模变压器的至少三个引脚位于相对于另一个引脚的位置，使得封装尺寸最小化。

公开(公告)号：US08196016B1

公开(公告)日：2012-06-05

申请号：US13190288

申请日：2011-07-25

申请人： Paul Langner ,  Ramin Shirani

发明人： Paul Langner ,  Ramin Shirani

IPC分类号： H03M13/00

CPC分类号： H03M13/11 ,  H03M13/1108 ,  H03M13/1142 ,  H03M13/3707 ,  H03M13/3738

摘要： Trapping set decoding for transmission frames is disclosed. In one aspect, a trapping set decoder includes a detector including an input to receive a decoded codeword and including circuitry to detect the presence of one or more trapping sets of bits in the decoded codeword. A selection processor is coupled to the detector to select one from a group of trapping sets and correct one or more bits in the decoded codeword based on statistical measures associated with the one or more trapping sets of bits.

摘要翻译： 公开了用于传输帧的陷阱集合解码。 一方面，捕获集合解码器包括检测器，其包括用于接收解码码字的输入，并且包括用于检测解码码字中一个或多个捕获位组的存在的电路。 选择处理器耦合到检测器以从一组陷阱集合中选择一个，并且基于与一个或多个陷阱集合相关联的统计量度来校正解码码字中的一个或多个比特。

公开(公告)号：US07675450B1

公开(公告)日：2010-03-09

申请号：US12139447

申请日：2008-06-13

申请人： Ali Tabatabaei ,  Ramin Farjadrad

发明人： Ali Tabatabaei ,  Ramin Farjadrad

IPC分类号： H03M1/66

CPC分类号： H03M1/682 ,  H03M1/0682 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747

摘要： A digital-to-analog converter (DAC) configured to operate in high frequency and/or high resolution environments. The DAC has a segmented architecture comprising one or more least significant bit (LSB) thermometer sub-converters and one or more most significant bit (MSB) thermometer sub-converters. A binary converter can also be added. The LSB and MSB thermometer sub-converters include cell pairs with a main cell and a dummy cell. The main cell switches according to actual data, drawing power from a voltage source at each transition. To maintain a consistent voltage level at the output, the dummy cell creates a transition to draw power from the voltage source responsive to a lack of transition in the main cell. Each cell pair has a dedicated voltage source. Also, the MSB thermometer sub-converter can include a load matching circuit to match the parasitic capacitance of the LSB thermometer sub-converter at an output.

摘要翻译： 配置为在高频和/或高分辨率环境中工作的数模转换器（DAC）。 DAC具有包括一个或多个最低有效位（LSB）温度计子转换器和一个或多个最高有效位（MSB）温度计子转换器）的分段架构。 还可以添加二进制转换器。 LSB和MSB温度计子转换器包括具有主单元和虚设单元的单元对。 主电池根据实际数据切换，每个转换时从电压源抽取功率。 为了在输出端保持一致的电压电平，虚拟电池产生一个转换，以响应于主电池中的过渡不足而从电压源吸取功率。 每个单元对具有专用电压源。 此外，MSB温度计子转换器可以包括负载匹配电路，以匹配LSB温度计子转换器在输出端的寄生电容。

公开(公告)号：US07663412B1

公开(公告)日：2010-02-16

申请号：US11451220

申请日：2006-06-12

申请人： Ramin Farjadrad

发明人： Ramin Farjadrad

IPC分类号： G05F3/20 ,  H03K17/60 ,  H03K17/687

CPC分类号： G05F3/262

摘要： A circuit is provided that (in one implementation) includes a first transistor having a first drain terminal, first gate terminal, and a first source terminal. The first drain terminal is connected to the first gate terminal, the first source terminal is connected to a first voltage. The circuit further includes a second transistor having a second drain terminal, second gate terminal, and a second source terminal. The second gate terminal is connected to both the first gate terminal and the first drain terminal, and the second source terminal is connected to the first voltage. The circuit further includes a third transistor having a third drain terminal, a third gate terminal, and a third source terminal. The third drain terminal is connected to the first drain terminal, and the third source terminal is connected to both the third gate terminal and a second voltage that is lower than the first voltage.

摘要翻译： 提供一种电路（在一个实施方式中）包括具有第一漏极端子，第一栅极端子和第一源极端子的第一晶体管。 第一漏极端子连接到第一栅极端子，第一源极端子连接到第一电压。 电路还包括具有第二漏极端子，第二栅极端子和第二源极端子的第二晶体管。 第二栅极端子连接到第一栅极端子和第一漏极端子，并且第二源极端子连接到第一电压。 电路还包括具有第三漏极端子，第三栅极端子和第三源极端子的第三晶体管。 第三漏极端子连接到第一漏极端子，第三源极端子连接到第三栅极端子和低于第一电压的第二电压。

公开(公告)号：US07583724B2

公开(公告)日：2009-09-01

申请号：US11006329

申请日：2004-12-06

申请人： Ramin Shirani

发明人： Ramin Shirani

IPC分类号： H04B1/38 ,  H04L5/16 ,  H04L1/00

CPC分类号： H04B3/235 ,  H04B3/143 ,  H04B3/32

摘要： A signal processing system includes an AGC and pre-echo cancellation system for receiving an analog signal, amplifying signal magnitude (over all frequencies) to a pre-determined level by AGC, and removing the immediate transmit pulse from this received signal by pre-echo canceller to provide a second analog signal. The signal processing system also includes a summer for receiving the analog signal; a feed forward equalization (FFE) unit for receiving a signal from the summer; and a slicer for receiving a signal from the FFE unit and providing an output signal. The signal processing system also includes an Echo and NEXT or FEXT cancellation system for receiving the output signal and for providing a signal to the summer for canceling the echo and crosstalk in the signal processing system. The Echo and crosstalk components associated with a signal processing system can be subtracted prior to the FFE.

摘要翻译： 信号处理系统包括用于接收模拟信号的AGC和预回波消除系统，通过AGC将信号幅度（在所有频率上）放大到预定电平，并且通过预回波从该接收信号中去除立即发射脉冲 消除器提供第二模拟信号。 信号处理系统还包括用于接收模拟信号的加法器; 用于从夏天接收信号的前馈均衡（FFE）单元; 以及用于从FFE单元接收信号并提供输出信号的限幅器。 信号处理系统还包括用于接收输出信号的Echo和NEXT或FEXT消除系统，并且用于向夏天提供信号以消除信号处理系统中的回声和串扰。 可以在FFE之前减去与信号处理系统相关的回波和串扰分量。

公开(公告)号：US07221196B2

公开(公告)日：2007-05-22

申请号：US10993107

申请日：2004-11-18

申请人： Ramin Shirani

发明人： Ramin Shirani

IPC分类号： H03K3/00

CPC分类号： H04L25/028 ,  H03K17/6871 ,  H03K2217/0036 ,  H04L25/4917

摘要： A low-power multi-level pulse amplitude modulation (PAM) line driver using variable resistors is disclosed for transmitting digital data over controlled-impedance transmission lines. This invention discloses the design of a multi-level PAM driver for high-speed wireline communication, with up to four times improvement in power efficiency over conventional drivers. Two key requirements for high-speed line drivers are first generating the target voltage level onto the controlled-impedance line, and second being impedance matched to the line itself to eliminate signal reflections from the transmitter back to the line. The driver in accordance with the present invention satisfies both of these requirements at very high power efficiency.

摘要翻译： 公开了一种使用可变电阻器的低功率多电平脉冲幅度调制（PAM）线路驱动器，用于通过受控阻抗传输线传输数字数据。 本发明公开了用于高速有线通信的多级PAM驱动器的设计，与常规驱动器相比，功率效率提高了四倍。 高速线路驱动器的两个关键要求是首先在受控阻抗线上产生目标电压电平，其次是与线路本身阻抗匹配，以消除发射机返回线路的信号反射。 根据本发明的驱动器以非常高的功率效率满足这两个要求。