公开(公告)号：US11119967B1

公开(公告)日：2021-09-14

申请号：US15083041

申请日：2016-03-28

申请人： Aquantia Corporation

发明人： Paul Langner

IPC分类号： G06F13/42 ,  G06F13/16

摘要： A system including an Ethernet transceiver PHY and a network device is disclosed. The Ethernet transceiver PHY includes register circuitry to store information associated with operating characteristics of the PHY. The network device couples to the Ethernet transceiver PHY in a closed system architecture and includes a system processor and an MDIO interface. The MDIO interface interacts with the PHY register circuitry during a normal operating mode. The system includes system interface circuitry to receive requests for accessing the register circuitry in a debug operating mode. The requests are generated external to the closed system architecture.

公开(公告)号：US10892880B1

公开(公告)日：2021-01-12

申请号：US15228161

申请日：2016-08-04

申请人： Aquantia Corporation

发明人： Kamal Dalmia

IPC分类号： H04L5/14 ,  G06F1/3203 ,  H04B1/40 ,  H04L12/40

摘要： In present embodiments, operation methods and apparatus for reducing power consumption in a 10GBASE-T transceiver circuit having transmit circuitry and receive circuitry for coupling to a plurality of physical channels are provided to transmit first data with the transmit circuitry in a first direction, receive second data with the receive circuitry in a second direction opposite to the first direction, identify an end-of-data indicator associated with the second data, and deactivate the receive circuitry in response to the end-of-data indicator. Preferably, in some embodiments, the receive circuitry is selectively switched off to reduce power consumption.

公开(公告)号：US10063341B1

公开(公告)日：2018-08-28

申请号：US15175516

申请日：2016-06-07

申请人： Aquantia Corporation

发明人： Ramin Farjadrad ,  Paul Langner ,  Hossein Sedarat ,  Ramin Shirani ,  Kamal Dalmia

IPC分类号： H04L1/00 ,  H04L12/811 ,  H04L12/825 ,  H04L12/931 ,  G06F11/10 ,  H03M13/11

CPC分类号： H04L1/0005 ,  G06F11/10 ,  H03M13/1102 ,  H04L1/0002 ,  H04L1/0003 ,  H04L1/0033 ,  H04L1/0036 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0058 ,  H04L47/25 ,  H04L47/38 ,  H04L49/351

摘要： Methods and apparatus for transmitting Ethernet data along an Ethernet link with a BASE-T transceiver are disclosed. One exemplary BASE-T Ethernet transceiver includes an Ethernet data framing module having an input interface to receive Ethernet block data bits at a first data rate. Logic associates the Ethernet block data bits with an auxiliary bit and a number of zero bits. An error encoder is coupled to the logic to encode all of the data bits, auxiliary bit and zero bits into an error encoded transport frame having plural error check bits. A symbol mapper receives the error encoded transport frame and transforms the error encoded transport frame into multiple symbols. A transmitter coupled to the symbol mapper transmits the multiple symbols over an Ethernet link at one of a selection of symbol rates. The data rate of data transmitted over the Ethernet link is based on the number of zero bits.

公开(公告)号：US09001872B1

公开(公告)日：2015-04-07

申请号：US13671132

申请日：2012-11-07

申请人： Aquantia Corporation

发明人： Ramin Farjadrad ,  Paul Langner ,  Hossein Sedarat ,  Ramin Shirani

IPC分类号： H04B1/38 ,  H04L12/931

CPC分类号： H04L1/0002 ,  H04L47/25 ,  H04L47/38 ,  H04L49/351

摘要： Methods and apparatus for transferring data along a link with a 10GBASE-T transceiver at a variable data rate are disclosed. One exemplary method includes detecting a link quality metric; and selecting a symbol transmission rate and a data modulation scheme based on the detected link quality metric. In many implementations, for a selected symbol transmission rate, if the detected link quality metric is less than a link quality threshold, then the selecting of the data modulation scheme is performed such that a data bit per symbol value represented by the selected data modulation scheme is decreased by at least ½ data bit per symbol. The selected symbol transmission rate and the selected modulation together represent a selectable data rate from a selection of data rates.

摘要翻译： 公开了以可变数据速率沿着具有10GBASE-T收发器的链路传送数据的方法和装置。 一种示例性方法包括检测链路质量度量; 以及基于检测到的链路质量度量来选择符号传输速率和数据调制方案。 在许多实施方案中，对于所选择的符号传输速率，如果检测到的链路质量度量小于链路质量阈值，则执行数据调制方案的选择，使得由所选择的数据调制方案表示的每符号值的数据比特 每符号减少至少1/2个数据位。 选择的符号传输速率和所选择的调制一起表示来自数据速率选择的可选数据速率。

公开(公告)号：US08891595B1

公开(公告)日：2014-11-18

申请号：US13790333

申请日：2013-03-08

申请人： Aquantia Corporation

发明人： Ramin Farjadrad ,  Michael Brown

IPC分类号： H04B1/38 ,  H04B1/04

CPC分类号： H04B1/0475 ,  H04L12/10 ,  H04L12/413 ,  H04L25/0266 ,  H04L25/0272 ,  H04L25/028

摘要： An integrated circuit device is disclosed. The integrated circuit device includes a differential driver to generate a differential signal having true and complement signal components that exhibit a relative timing relationship. A transmission port provides an interface for delivering the differential signal to a transmission medium. A common mode detection circuit detects a common mode signal associated with the differential signal. Control circuitry generates a control signal based on the detected common mode signal. Timing circuitry adjusts the relative timing between the true and the complement signal components based on the control signal.

摘要翻译： 公开了一种集成电路器件。 集成电路器件包括差分驱动器，用于产生具有呈现相对定时关系的真实和补码信号分量的差分信号。 传输端口提供用于将差分信号传送到传输介质的接口。 共模检测电路检测与差分信号相关联的共模信号。 控制电路基于检测到的共模信号产生控制信号。 定时电路根据控制信号调整真和补码信号分量之间的相对定时。

公开(公告)号：US08804582B1

公开(公告)日：2014-08-12

申请号：US13974551

申请日：2013-08-23

申请人： Aquantia Corporation

发明人： Dimitry Taich ,  Jose Tellado

IPC分类号： H04B1/44

CPC分类号： H04L12/10

摘要： An apparatuses and methods of setting power back-off of a master transceiver and a slave transceiver is disclosed. One example of a method includes the master transceiver determining a master power back-off, and the slave transceiver determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off. One example of an apparatus includes a master transceiver and slave transceiver system. The slave transceiver is connected to the master transceiver through a cable. The master transceiver includes means for determining a master power back-off. The slave transceiver includes means for determining a slave power back-off based on signals received from the master transceiver, and based on the master power back-off.

摘要翻译： 公开了一种设置主收发器和从属收发器的功率回退的装置和方法。 方法的一个示例包括主收发器确定主功率回退，并且从收发器基于从主收发器接收的信号以及基于主功率回退确定从功率回退。 设备的一个示例包括主收发器和从收发器系统。 从设备收发器通过电缆连接到主收发器。 主收发器包括用于确定主功率回退的装置。 从属收发器包括用于基于从主收发器接收的信号以及基于主功率回退确定从功率回退的装置。

公开(公告)号：US11139800B1

公开(公告)日：2021-10-05

申请号：US16419625

申请日：2019-05-22

申请人： Aquantia Corporation

发明人： Oliver Weiss ,  Martin Broich

IPC分类号： H03H21/00 ,  H03H17/02 ,  H03H17/00

摘要： A receiver circuit is disclosed. The receiver circuit includes a multi-PAM input circuit to receive a multi-PAM input symbol. The input symbol exhibits one of multiple threshold levels during a sampling period. The threshold levels correspond to a set of M-bit two's-complement values within a defined set of threshold values. An adaptive filtering circuit includes a first transcoder to transcode the set of M-bit two's-complement values to a set of N-bit values, where N

公开(公告)号：US11088876B1

公开(公告)日：2021-08-10

申请号：US16365510

申请日：2019-03-26

申请人： Aquantia Corporation

发明人： Ramin Farjadrad

IPC分类号： H04L13/02 ,  H04L25/02 ,  G06F13/40 ,  H04L7/00

摘要： A configurable serial link interface circuit is disclosed. The configurable serial link interface includes a first transceiver for coupling to a first serial link. The first transceiver includes a first transmit circuit to selectively drive first transmit data along the first serial link and a first receive circuit. the first receive circuit selectively receives first receive data along the first serial link. The interface includes a second transceiver for coupling to a second serial link. The second transceiver includes a second transmit circuit to selectively drive second transmit data along the second serial link, a second receive circuit to selectively receive second receive data along the second serial link, and control circuitry to control the selectivity of the first transmit circuit, the second transmit circuit, the first receive circuit and the second receive circuit. For a first mode of operation, the control circuitry configures the first and second transceivers to define a dual-duplex architecture. For a second mode of operation, the control circuitry configures the first and second transceivers to define a single-duplex architecture.

公开(公告)号：US11055244B1

公开(公告)日：2021-07-06

申请号：US16419585

申请日：2019-05-22

申请人： Aquantia Corporation

发明人： Paul Langner ,  Simon Edelhaus

IPC分类号： G06F13/38 ,  G06F13/42

摘要： An input/output (I/O) interface system for computing devices is disclosed. The I/O interface system includes an externally-engageable USB-C interface connector. A first I/O protocol controller circuit couples to the USB-C interface connector via multiple bidirectional serial lanes. Each of the bidirectional serial lanes transfers a single serial stream of data in a simultaneously bidirectional manner. A second I/O protocol controller circuit couples to the USB-C interface connector via multiple unidirectional serial lanes. Each of the unidirectional serial lanes transfers a single serial stream of data in a unidirectional manner. Mode control circuitry selects between the first I/O protocol controller circuit and the second I/O protocol controller circuit for data transfers with the USB-C interface connector based on a detected signaling media externally connected to the USB-C interface connector.

公开(公告)号：US10999124B1

公开(公告)日：2021-05-04

申请号：US14961810

申请日：2015-12-07

申请人： Aquantia Corporation

发明人： Hossein Sedarat ,  Ramin Farjadrad ,  Kamal Dalmia ,  Ramin Shirani ,  Seid Alireza Razavi Majomard

IPC分类号： H04L12/24 ,  H04L12/825

摘要： A method for fast link recovery for an Ethernet link is disclosed. The method includes detecting a drop in link quality and performing a first fast retrain sequence, including determining and exchanging THP coefficients based on the drop in link quality. If the performed fast retrain fails to recover the link, a data rate associated with the link is reduced, and a second fast retrain sequence performed.