公开(公告)号：US20100253563A1

公开(公告)日：2010-10-07

申请号：US12729291

申请日：2010-03-23

Applicant: Venkatesh Teeka Srinivasa SHETTY ,  Govind Kulkarni ,  Srinivasan Chakravarthy ,  Sumeet Mathur

Inventor： Venkatesh Teeka Srinivasa SHETTY ,  Govind Kulkarni ,  Srinivasan Chakravarthy ,  Sumeet Mathur

IPC: H03M1/66 ,  H05K9/00

CPC classification number: H03M1/0612 ,  H01L27/0207 ,  H03M1/68 ,  H03M1/804

Abstract: A method and system for capacitor based digital to analog converter design layout for high speed analog to digital converter are provided. The method includes arranging a plurality of metal plates to form the capacitor. Each of the plurality of metal plates includes a driven plate and a common plate. The method also includes generating a plurality of interconnects in the common plate and extending the driven plate over the plurality of interconnects. Further, the method includes shielding the common plate by the driven plate. The system includes an analog to digital converter. The analog to digital converter also includes capacitor based digital to analog converter and digital logic for controlling digital operations in the analog to digital converter. The capacitor based digital to analog converter includes a plurality of capacitors, and a comparator for comparing the analog output from the digital to analog converter with a ground potential.

Abstract translation: 提供了一种用于高速模数转换器的基于电容器的数模转换器设计布局的方法和系统。 该方法包括布置多个金属板以形成电容器。 多个金属板中的每一个包括从动板和公共板。 该方法还包括在公共板中产生多个互连件并且在多个互连件上延伸从动板。 此外，该方法包括通过从动板屏蔽公共板。 该系统包括一个模数转换器。 模数转换器还包括基于电容的数模转换器和用于控制模数转换器中的数字操作的数字逻辑。 基于电容器的数模转换器包括多个电容器，以及用于将来自数模转换器的模拟输出与地电势进行比较的比较器。

公开(公告)号：US20090278516A1

公开(公告)日：2009-11-12

申请号：US12436136

申请日：2009-05-06

Applicant: Hrishikesh BHAGWAT ,  Rupak GHAYAL ,  Saumitra SINGH ,  Pawan GUPTA ,  Prakash EASWARAN

Inventor： Hrishikesh BHAGWAT ,  Rupak GHAYAL ,  Saumitra SINGH ,  Pawan GUPTA ,  Prakash EASWARAN

IPC: G05F1/10

CPC classification number: H02M3/1588 ,  Y02B70/1466

Abstract: A transient recovery circuit for switching devices. The transient recovery circuit includes a detecting circuit for detecting a rapid transient in an output voltage of a switching device by detecting a rate of the output voltage transient; an auxiliary controlling circuit in a feedback loop of the switching device for correcting the output voltage by changing a bandwidth of the feedback loop if the rapid transient is detected; and an initializing circuit for initializing the feedback loop to expected operating points in a continuous conduction mode after correcting the output voltage.

Abstract translation: 用于开关器件的瞬态恢复电路。 瞬态恢复电路包括检测电路，用于通过检测输出电压瞬变的速率来检测开关装置的输出电压中的快速瞬变; 所述开关装置的反馈环路中的辅助控制电路，用于通过在检测到所述快速瞬变时改变所述反馈回路的带宽来校正所述输出电压; 以及用于在校正输出电压之后将连续导通模式中的反馈回路初始化为期望工作点的初始化电路。

公开(公告)号：US07570181B2

公开(公告)日：2009-08-04

申请号：US11760780

申请日：2007-06-10

Applicant: Sundararajan Krishnan ,  C. Srinivasan

Inventor： Sundararajan Krishnan ,  C. Srinivasan

IPC: H03M1/06

CPC classification number: H03M1/0607 ,  H03M1/12

Abstract: Methods and systems for input voltage droop compensation in video/graphics front-end systems. The method of an embodiment of the invention captures input voltage information supplied to an Analog-to-Digital Converter (ADC) operatively coupled to a bypass capacitor in a video/graphics front-end system; calculates a droop in the input voltage in ADC due to a charge sharing between an input sampling capacitor of the ADC and the bypass capacitor; and compensates for the value of the bypass capacitor using an output of the ADC. Embodiments of the invention provide an improved freedom in the choice of off-chip bypass capacitance in video/graphics front-end systems.

Abstract translation: 视频/图形前端系统中输入电压下降补偿的方法和系统。 本发明的实施例的方法捕获提供给在视频/图形前端系统中可操作地耦合到旁路电容器的模数转换器（ADC）的输入电压信息; 由于ADC的输入采样电容和旁路电容之间的电荷共享，在ADC中计算输入电压的下降; 并使用ADC的输出补偿旁路电容的值。 本发明的实施例提供了在视频/图形前端系统中选择片外旁路电容的改进的自由度。

公开(公告)号：US20130021092A1

公开(公告)日：2013-01-24

申请号：US13009868

申请日：2011-01-20

Applicant: Prasun Kali BHATTACHARYYA ,  Sumanth Chakkirala ,  Prakash Easwaran

Inventor： Prasun Kali BHATTACHARYYA ,  Sumanth Chakkirala ,  Prakash Easwaran

IPC: H03K5/00

CPC classification number: H03H7/0153 ,  H03H7/06 ,  H03H11/12 ,  H03H2210/012 ,  H03H2210/028

Abstract: An ultra low cut-off frequency filter. A filter circuit includes a control circuit responsive to an input signal and a feedback signal to generate a control signal. The filter circuit includes a controllable resistor coupled to the control circuit. The controllable resistor is responsive to a reference signal and the control signal to generate the feedback signal. The filter circuit includes a feedback path coupled to the control circuit and the controllable resistor to couple the feedback signal from the controllable resistor to the control circuit, thereby removing noise from at least one of the input signal and the reference signal, and preventing voltage error in the filter circuit.

Abstract translation: 超低截止频率滤波器。 滤波电路包括响应于输入信号和反馈信号的控制电路以产生控制信号。 滤波器电路包括耦合到控制电路的可控电阻器。 可控电阻响应于参考信号和控制信号以产生反馈信号。 滤波器电路包括耦合到控制电路和可控电阻器的反馈路径，以将来自可控电阻器的反馈信号耦合到控制电路，从而从输入信号和参考信号中的至少一个消除噪声，并且防止电压误差 在滤波电路中。

公开(公告)号：US20100164606A1

公开(公告)日：2010-07-01

申请号：US12463390

申请日：2009-05-09

Applicant: Prakash EASWARAN ,  Prasenjit BHOWMIK ,  Sumeet MATHUR

Inventor： Prakash EASWARAN ,  Prasenjit BHOWMIK ,  Sumeet MATHUR

IPC: G05F1/10

CPC classification number: G05F3/26 ,  H03F1/301

Abstract: A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes.

Abstract translation: 用于偏置MOS晶体管的方法包括将来自放大器级的输入信号AC耦合到MOS晶体管的栅极。 该方法包括将一对相反并联配置的二极管连接到偏置晶体管和电流源。 此外，该方法包括通过偏置晶体管和电流源产生DC偏置电压。 该方法还包括通过钳位电路将偏置晶体管的漏极处的电压钳位到固定电压。 此外，该方法包括通过一对二极管将DC偏置电压耦合到MOS晶体管的栅极。

公开(公告)号：US07548104B2

公开(公告)日：2009-06-16

申请号：US11760784

申请日：2007-06-10

Applicant: Prasenjit Bhowmik ,  Sundararajan Krishnan ,  G. Sriram

Inventor： Prasenjit Bhowmik ,  Sundararajan Krishnan ,  G. Sriram

IPC: H03H11/26

CPC classification number: H03K5/1565 ,  H03H11/265 ,  H03K5/133 ,  H03K2005/00045

Abstract: A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.

Abstract translation: 公开了一种包括具有改善的增益和内置的占空比失真控制的相同延迟单元序列的延迟线及其方法。 序列的每个延迟单元包括电流源，四个晶体管和负载电容器。 电流源的栅极接收控制延迟单元的延迟的电压偏置。 第一晶体管的漏极连接到电流源的漏极。 第一和第二晶体管栅极接收输入时钟信号。 第二晶体管漏极连接到电流源的源极。 第三晶体管栅极和负载电容器也连接到电流源的漏极。 第四晶体管漏极连接到第三晶体管漏极。 第四晶体管栅极耦合到用于占空比失真控制的第二连续延迟单元的输出。

公开(公告)号：US20130127522A1

公开(公告)日：2013-05-23

申请号：US13301778

申请日：2011-11-22

Applicant: Anand Mohan ,  Sumeet Mathur

Inventor： Anand Mohan ,  Sumeet Mathur

IPC: G05F3/02

CPC classification number: H02M3/07

Abstract: An electrical system for generating arbitrary voltage waveform includes a power supply unit for providing a supply voltage to the electrical system. One or more charge pumps are in electrical communication with the power supply unit. Each charge pump generates a voltage. The electrical system also includes a plurality of switches, a first switch among the plurality of switches coupled between a ground and an output terminal, other switches among the plurality of switches coupled between the one or more charge pumps and the output terminal. A control circuit is in electrical communication with the power supply unit, the plurality of switches and the one or more charge pumps, and is operable to control the voltage generated by the each charge pump and the plurality of switches. Voltages from the one or more charge pumps additively result in a variable output voltage that generates an arbitrary voltage waveform.

Abstract translation: 用于产生任意电压波形的电气系统包括用于向电气系统提供电源电压的电源单元。 一个或多个电荷泵与电源单元电连通。 每个电荷泵产生一个电压。 电气系统还包括多个开关，耦合在地和输出端之间的多个开关中的第一开关，耦合在一个或多个电荷泵与输出端之间的多个开关中的其它开关。 控制电路与电源单元，多个开关和一个或多个电荷泵电连通，并且可操作以控制由每个电荷泵和多个开关产生的电压。 来自一个或多个电荷泵的电压相加地导致产生任意电压波形的可变输出电压。

公开(公告)号：US20120319789A1

公开(公告)日：2012-12-20

申请号：US13301806

申请日：2011-11-22

Applicant: Prasenjit Bhowmik ,  Rishi Mathur ,  Sriram Ganesan ,  Sunil Rajan

Inventor： Prasenjit Bhowmik ,  Rishi Mathur ,  Sriram Ganesan ,  Sunil Rajan

IPC: H03K3/02

CPC classification number: H03K4/502 ,  H03K3/0231

Abstract: A relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation includes a first current source that generates charging current, a second current source coupled to the first current source to generate reference voltage, a resistor coupled to the second current source to enable generation of the reference voltage, a capacitor coupled to the first current source that is charged based on the charging current, a comparator responsive to voltage corresponding to the capacitor and the reference voltage to generate output voltage, a peak detector coupled to the capacitor to generate peak voltage, an error detector coupled to the peak detector and the second current source to generate an error based on the peak voltage and the reference voltage, and a controller coupled to the error detector to control one of the charging current, offset voltage input to the comparator, and capacitance of the capacitor.

Abstract translation: 具有降低的振荡频率对比较器延迟变化的灵敏度的张弛振荡器电路包括产生充电电流的第一电流源，耦合到第一电流源以产生参考电压的第二电流源，耦合到第二电流源的电阻器，以产生 参考电压耦合到基于充电电流而被充电的电容器，响应于与电容器相对应的电压的比较器和参考电压以产生输出电压;峰值检测器，耦合到电容器以产生峰值 电压，耦合到所述峰值检测器和所述第二电流源的误差检测器，以基于所述峰值电压和所述参考电压产生误差;以及控制器，耦合到所述误差检测器以控制输入到所述电压的所述充电电流， 比较器和电容器的电容。

公开(公告)号：US08242762B2

公开(公告)日：2012-08-14

申请号：US12436136

申请日：2009-05-06

Applicant: Hrishikesh Bhagwat ,  Rupak Ghayal ,  Saumitra Singh ,  Pawan Gupta ,  Prakash Easwaran

Inventor： Hrishikesh Bhagwat ,  Rupak Ghayal ,  Saumitra Singh ,  Pawan Gupta ,  Prakash Easwaran

IPC: G05F1/575

CPC classification number: H02M3/1588 ,  Y02B70/1466

Abstract: A transient recovery circuit for switching devices. The transient recovery circuit includes a detecting circuit for detecting a rapid transient in an output voltage of a switching device by detecting a rate of the output voltage transient; an auxiliary controlling circuit in a feedback loop of the switching device for correcting the output voltage by changing a bandwidth of the feedback loop if the rapid transient is detected; and an initializing circuit for initializing the feedback loop to expected operating points in a continuous conduction mode after correcting the output voltage.

Abstract translation: 用于开关器件的瞬态恢复电路。 瞬态恢复电路包括检测电路，用于通过检测输出电压瞬变的速率来检测开关装置的输出电压中的快速瞬变; 所述开关装置的反馈环路中的辅助控制电路，用于通过在检测到所述快速瞬变时改变所述反馈回路的带宽来校正所述输出电压; 以及用于在校正输出电压之后将连续导通模式中的反馈回路初始化为期望工作点的初始化电路。

公开(公告)号：US08149152B2

公开(公告)日：2012-04-03

申请号：US12729291

申请日：2010-03-23

Applicant: Venkatesh Teeka Srinivasa Shetty ,  Govind Kulkarni ,  Srinivasan Chakravarthy ,  Sumeet Mathur

Inventor： Venkatesh Teeka Srinivasa Shetty ,  Govind Kulkarni ,  Srinivasan Chakravarthy ,  Sumeet Mathur

IPC: H03M1/66

CPC classification number: H03M1/0612 ,  H01L27/0207 ,  H03M1/68 ,  H03M1/804

Abstract: A method and system for capacitor based digital to analog converter design layout for high speed analog to digital converter are provided. The method includes arranging a plurality of metal plates to form the capacitor. Each of the plurality of metal plates includes a driven plate and a common plate. The method also includes generating a plurality of interconnects in the common plate and extending the driven plate over the plurality of interconnects. Further, the method includes shielding the common plate by the driven plate. The system includes an analog to digital converter. The analog to digital converter also includes capacitor based digital to analog converter and digital logic for controlling digital operations in the analog to digital converter. The capacitor based digital to analog converter includes a plurality of capacitors, and a comparator for comparing the analog output from the digital to analog converter with a ground potential.

Abstract translation: 提供了一种用于高速模数转换器的基于电容器的数模转换器设计布局的方法和系统。 该方法包括布置多个金属板以形成电容器。 多个金属板中的每一个包括从动板和公共板。 该方法还包括在公共板中产生多个互连件并且在多个互连件上延伸从动板。 此外，该方法包括通过从动板屏蔽公共板。 该系统包括一个模数转换器。 模数转换器还包括基于电容的数模转换器和用于控制模数转换器中的数字操作的数字逻辑。 基于电容器的数模转换器包括多个电容器，以及用于将来自数模转换器的模拟输出与地电势进行比较的比较器。