High resolution clock signal generator

    公开(公告)号:US08504867B2

    公开(公告)日:2013-08-06

    申请号:US12892854

    申请日:2010-09-28

    申请人: Eric B Kushnick

    发明人: Eric B Kushnick

    IPC分类号: G06F1/24

    摘要: A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period TP to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of TP/N seconds over a range spanning TP seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning TP seconds with a delay resolution of TP/M seconds to provide pulses of the clock signal with a timing resolution of TP/(M*N) seconds when the integers N and M are relatively prime.

    High resolution clock signal generator
    2.
    发明授权
    High resolution clock signal generator 有权
    高分辨率时钟信号发生器

    公开(公告)号:US07805628B2

    公开(公告)日:2010-09-28

    申请号:US09824898

    申请日:2001-04-02

    申请人: Eric B. Kushnick

    发明人: Eric B. Kushnick

    IPC分类号: G06F1/08

    摘要: A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period Tp to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of Tp/N seconds over a range spanning Tp seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning Tp seconds with a delay resolution of TP/M seconds to provide pulses of the clock signal with a timing resolution of Tp/(M*N) seconds when the integers N and M are relatively prime.

    摘要翻译: 具有串联连接的第一和第二粗略延迟电路的时钟信号发生器延迟具有周期Tp的参考信号的脉冲以产生时钟信号的脉冲。 第一粗延迟电路在跨越Tp秒的范围内以Tp / N秒的延迟分辨率延迟参考信号的脉冲,以产生输出信号的脉冲。 第二粗延迟电路在延迟分辨率为TP / M秒的范围内跨越Tp秒的范围来延迟第一粗延迟电路的输出信号的脉冲,以提供时钟信号的脉冲,其具有Tp /(M * N )秒,当整数N和M相对于素数时。

    Apparatus for jitter testing an IC
    3.
    发明授权
    Apparatus for jitter testing an IC 失效
    用于抖动测试IC的装置

    公开(公告)号:US07627790B2

    公开(公告)日:2009-12-01

    申请号:US10992955

    申请日:2004-11-18

    摘要: An integrated circuit tester channel includes an integrated circuit (IC) for adding a programmably controlled amount of jitter to a digital test signal to produce a DUT input signal having a precisely controlled jitter pattern. The IC also measures periods between selected edges of the same or different ones of the DUT output signal, the DUT input signal, and a reference clock signal. Additionally, when the DUT input and output signals convey repetitive patterns, the IC can measure the voltage of the DUT input out output signal as selected points within the pattern by comparing it to an adjustable reference voltage. Processing circuits external to the IC program the IC to provide a specified amount of jitter to the test signal, control the measurements carried out by the measurement circuit, and process measurement data to determine the amount of jitter and other characteristics of the DUT output signal, and to calibrate the jitter in the DUT input signal.

    摘要翻译: 集成电路测试器通道包括用于将可编程控制量的抖动添加到数字测试信号的集成电路(IC),以产生具有精确控制的抖动模式的DUT输入信号。 IC还测量DUT输出信号,DUT输入信号和参考时钟信号相同或不同的选定边沿之间的周期。 此外,当DUT输入和输出信号传送重复模式时,IC可以通过将DUT输入输出信号的电压与可调参考电压进行比较来测量DUT输出信号中的选定点。 处理电路外部IC程序IC为测试信号提供规定量的抖动,控制由测量电路进行的测量,并处理测量数据以确定DUT输出信号的抖动等特性, 并校准DUT输入信号中的抖动。

    System and method for test socket calibration using composite waveform
    4.
    发明授权
    System and method for test socket calibration using composite waveform 有权
    使用复合波形测试插座校准的系统和方法

    公开(公告)号:US07439728B1

    公开(公告)日:2008-10-21

    申请号:US11185569

    申请日:2005-07-19

    IPC分类号: G01R31/00

    CPC分类号: G01R31/3191

    摘要: A system and method for calibration of a test socket using a composite waveform. A group of input signal pins of test system are coupled together. A pin belonging to the group is selected as a pin under calibration. A first calibration edge is applied to the pin under calibration. After a delay, a group of complementary edges is applied to the remaining pins of the group. As a result of the coupling of the pins, a response comprising a reflected edge and a transmitted combined edge are produced, which overlap to form a composite waveform. A comparator is used to detect an observable feature in the composite waveform to obtain timing information with respect to the pin under calibration and the remaining pins of the group. Each pin may be analyzed in turn, and the group of pins calibrated using the acquired information.

    摘要翻译: 使用复合波形校准测试插座的系统和方法。 一组测试系统的输入信号引脚耦合在一起。 选择属于该组的引脚作为校准引脚。 第一个校准边沿在校准下施加到引脚。 延迟后,将一组互补的边缘应用于组的其余引脚。 作为引脚的耦合的结果,产生包括反射边缘和发射的组合边缘的响应,其重叠以形成复合波形。 比较器用于检测复合波形中的可观察特征,以获得关于校准引脚和组中剩余引脚的定时信息。 可以依次分析每个引脚,并且使用所获取的信息来校准引脚组。

    Reduced pin count test method and apparatus
    5.
    发明授权
    Reduced pin count test method and apparatus 失效
    引脚数减少测试方法和设备

    公开(公告)号:US07336066B2

    公开(公告)日:2008-02-26

    申请号:US10851454

    申请日:2004-05-21

    申请人: Burnell G. West

    发明人: Burnell G. West

    IPC分类号: G01R31/02 G01R31/28

    CPC分类号: G01R31/3172

    摘要: Testing of an electronic device is carried out by combining power and signal delivery on a single pair of wires. The power delivery is decoupled from the signal delivery, using inductors, so the device power supplied does not interfere with the test signals delivered from the device and the response signals delivered to the device. Further, simultaneous bidirectional signal paths are decoupled, using capacitors, so that the tester transceiver and the device transceiver are not damaged by the power delivered to the device on the same wires. A common fixture may be used to test a number of different types of wafers, independent of the topography, size, or power requirements of the devices on the wafers, resulting in a significant cost saving, because fixture design has become very expensive, in some cases costing more than the tester whose signals it is implemented to deliver.

    摘要翻译: 电子设备的测试是通过在一对电线上组合功率和信号传输来进行的。 功率输出与信号传输分离,使用电感器,因此提供的器件电源不会干扰从器件传送的测试信号和传送到器件的响应信号。 此外,同时的双向信号路径使用电容器去耦合,使得测试仪收发器和设备收发器不会因在相同导线上传送到设备的功率而损坏。 可以使用通用夹具来测试多种不同类型的晶片,而不考虑晶片上器件的形貌,尺寸或功率要求,导致显着的成本节省,因为夹具设计变得非常昂贵,在一些 这些案例的成本要高于其实施信号的测试仪。

    LRL VECTOR CALIBRATION TO THE END OF THE PROBE NEEDLES FOR NON-STANDARD PROBE CARDS FOR ATE RF TESTERS
    6.
    发明申请
    LRL VECTOR CALIBRATION TO THE END OF THE PROBE NEEDLES FOR NON-STANDARD PROBE CARDS FOR ATE RF TESTERS 失效
    用于ATE射频测试仪的非标准探头卡的探针末端的LRL矢量校准

    公开(公告)号:US20080036469A1

    公开(公告)日:2008-02-14

    申请号:US11463174

    申请日:2006-08-08

    IPC分类号: G01R35/00

    CPC分类号: G01R35/005

    摘要: A method and apparatus for radio frequency vector calibration of s-parameter measurements to the tips of the wafer probe needles of an automatic test equipment production tester. The method involves a modified Line-Reflect-Line (LRL) calibration routine that uses a Thru-Reflect-Line to LRL shift to eliminate the need for a precisely characterized reflect standard used during a conventional LRL calibration. The method further involves de-embedding the non-ideal effects of the non-zero length thru standard used during the calibration routine to improve measurement accuracy of the tester. The apparatus may involve the use of RF relays to allow multiple wafer probe needles to share RF test ports.

    摘要翻译: 一种用于对自动测试设备生产测试仪的晶片探针的尖端进行s参数测量的射频矢量校准的方法和装置。 该方法涉及一种修改的线路反射线(LRL)校准程序,其使用Thru-Reflect-Line进行LRL移位,以消除在常规LRL校准期间使用的精确表征的反射标准的需要。 该方法还涉及去除在校准程序期间使用的非零长度通过标准的非理想效果,以提高测试仪的测量精度。 该装置可以涉及使用RF继电器以允许多个晶片探针针体共享RF测试端口。

    Multi-domain execution of tests on electronic devices
    8.
    发明授权
    Multi-domain execution of tests on electronic devices 有权
    多域执行电子设备上的测试

    公开(公告)号:US07246026B2

    公开(公告)日:2007-07-17

    申请号:US11022148

    申请日:2004-12-21

    申请人: Lionel Gilet

    发明人: Lionel Gilet

    IPC分类号: G01R31/00 G01R31/14

    摘要: A device under test is divided into multiple test domains, and test conditions for each of the multiple test domains are defined separately, so that each test domain has its own test pattern, timing data, and other test conditions. Each test domain can start and stop independently, and run at different speeds. Further, triggers are used to specify how the tests executed in the different test domains interact and communicate with one another. Any test domain can generate or wait for a trigger from any other test domain (including the CPU).

    摘要翻译: 被测设备被分为多个测试域,并且分别定义了每个测试域的测试条件,以便每个测试域都有自己的测试模式,时序数据和其他测试条件。 每个测试域可以独立启动和停止,并以不同的速度运行。 此外,触发器用于指定在不同测试域中执行的测试如何相互交互并进行通信。 任何测试域都可以生成或等待任何其他测试域(包括CPU)的触发器。

    Knife edge tracking system and method
    10.
    发明授权
    Knife edge tracking system and method 失效
    刀刃追踪系统及方法

    公开(公告)号:US07227580B2

    公开(公告)日:2007-06-05

    申请号:US10719880

    申请日:2003-11-20

    IPC分类号: G03B7/00 G01R31/02

    CPC分类号: G01B11/028

    摘要: A system and method for automatically and accurately determining the exact location of a knife-edge, such as an edge of an optical shutter, so that it can be controlled automatically. In one aspect the system comprises a mechanized shutter coupled to a shutter controller that can automatically control the shutter's location and movement. According to one implementation of the shutter controller the system takes a first image at a first shutter position. The shutter is then moved a predetermined about and a second image is taken. Then, the pixels of each image are added in the direction perpendicular to the movement of the shutter, so as to provide two one-dimension functions. A linear difference of the functions is then taken, so as to obtain a one-dimensional linear difference function. A peak in the linear difference function is then identified as the location of the shutter.

    摘要翻译: 一种用于自动和准确地确定诸如光学快门的边缘的刀刃的确切位置的系统和方法,使得其可以被自动控制。 在一个方面,系统包括耦合到快门控制器的机械式快门,其可以自动控制快门的位置和移动。 根据快门控制器的一个实施方式,系统在第一快门位置拍摄第一图像。 然后将快门移动预定的大约和第二个图像。 然后,在与快门的移动垂直的方向上添加每个图像的像素,以提供两个一维功能。 然后获取函数的线性差,以获得一维线性差分函数。 然后将线性差函数中的峰值识别为快门的位置。