DETERMINING WHETHER AN OPERATING SYSTEM IN A MULTI-OPERATING SYSTEM COMPUTER SYSTEM IS ONLINE USING A WATCHDOG PROCESS

    公开(公告)号:US20240362029A1

    公开(公告)日:2024-10-31

    申请号:US18765148

    申请日:2024-07-05

    IPC分类号: G06F9/4401 G06F9/30 G06T1/20

    摘要: A computer system has a plurality of operating systems, each operating system including a graphics processing unit (GPU) driver; a GPU including GPU firmware for controlling the execution of tasks at the graphics processing unit and, for each operating system: a firmware state register modifiable by the GPU firmware and indicating whether the GPU firmware is online; an OS state register modifiable by a GPU driver and indicating whether the GPU driver is online; a memory management unit mediating access to GPU registers such that each operating system can access its respective registers but not those of other operating systems; One of the GPU drivers is a host GPU driver initialising the GPU and bringing the GPU firmware online. Each GPU driver submits tasks for processing only if its respective firmware state register indicates that the GPU firmware is online. The GPU processes tasks for an operating system if the respective OS state register of that operating system indicates that the GPU driver is online.

    Processor with hardware pipeline
    3.
    发明授权

    公开(公告)号:US12112197B2

    公开(公告)日:2024-10-08

    申请号:US17953821

    申请日:2022-09-27

    IPC分类号: G06F9/48 G06F9/46

    CPC分类号: G06F9/4881 G06F9/462

    摘要: A processor has a register bank to which software writes descriptors specifying tasks to be processed by a hardware pipeline. The register bank includes a plurality of register sets, each for holding the descriptor of a task. The processor includes a first selector operable to connect the execution logic to a selected one of the register sets and thereby enable the software to write successive ones of said descriptors to different ones of said register sets. The processor also includes a second selector operable to connect the hardware pipeline to a selected one of the register sets. The processor further comprises control circuitry configured to control the hardware pipeline to begin processing a current task based on the descriptor in a current one of the register sets while the software is writing the descriptor of another task to another of the register sets.

    METHODS AND SYSTEMS FOR PERFORMING A STANDARD DECONVOLUTION ON A GPU

    公开(公告)号:US20240320299A1

    公开(公告)日:2024-09-26

    申请号:US18591869

    申请日:2024-02-29

    IPC分类号: G06F17/16

    CPC分类号: G06F17/16

    摘要: Methods of implementing a standard deconvolution on a graphics processing unit, the standard deconvolution being representable as a direct convolution between an input tensor to the standard deconvolution and each of a plurality of a sub-filters, each sub-filter of the plurality of sub-filters comprising a subset of weights of a filter of the standard deconvolution. The methods comprising: receiving, at the graphics processing unit, the input tensor in a dense format; identifying, at the graphics processing unit, active positions of the received input tensor; performing, at the graphics processing unit, an indexed unfold operation on the input tensor based on the identified active positions to generate an input matrix comprising elements of the input tensor in each non-zero sub-window of the input tensor; and performing, at the graphics processing unit, a matrix multiplication between a weight matrix and the input matrix to generate an output matrix that comprises elements of an output tensor of the standard deconvolution that are based on the non-zero sub-windows of the input tensor.

    DATA INTEGRITY CHECKING
    6.
    发明公开

    公开(公告)号:US20240319272A1

    公开(公告)日:2024-09-26

    申请号:US18588819

    申请日:2024-02-27

    IPC分类号: G01R31/3185 G01R31/317

    摘要: A set of payload flip-flops receives an input instance of a payload, and outputs an output instance from which a first instance of an error check signal is generated. One or more error check flip-flops receive the first instance and output a second instance. The input payload instance is clocked into the payload flip-flops if a payload enable signal is asserted, and the first error-check signal instance is clocked into the error check flip-flops if an error check enable signal is asserted. The input payload instance is input to the set of payload flip-flops over two clock cycles, and the payload enable signal is asserted for the two clock cycles. The error check enable signal is asserted on the second cycle. The first instance of the error check signal is compared with the second instance and an error signal is asserted if they do not match.

    TESSELLATION METHODS AND SYSTEMS IN RAY TRACING

    公开(公告)号:US20240303905A1

    公开(公告)日:2024-09-12

    申请号:US18599607

    申请日:2024-03-08

    发明人: Peter Smith-Lacey

    IPC分类号: G06T15/06 G06T17/20

    摘要: A method of performing tessellation of a patch in a ray tracing system for rendering an image within a scene. The patch represents a portion of a surface of an object within the scene, and the object is defined in 3D space using a first space-coordinate system. A bounding volume that contains the patch is determined, and determining whether a ray intersects the bounding volume. In response to determining that the ray intersects the bounding volume, and in dependence on tessellation indications associated with the patch, the patch is subdivided one or more times to obtain a plurality of patch sub-units, wherein one or more of the patch sub-units does not represent a primitive. The method includes, subsequent to the subdividing of the patch, determining that at least one of the patch sub-units comprises a primitive, and performing an intersection test between the ray and the primitive for use in rendering the image of the scene.

    Coding blocks of pixels
    10.
    发明授权

    公开(公告)号:US12073593B2

    公开(公告)日:2024-08-27

    申请号:US17870623

    申请日:2022-07-21

    发明人: Rostam King

    IPC分类号: G06T9/00 G06T15/04

    CPC分类号: G06T9/00 G06T15/04

    摘要: A method and decoding unit for decoding a compressed data structure that encodes a set of Haar coefficients for a 2×2 quad of pixels of a block of pixels. The set of Haar coefficients comprises a plurality of differential coefficients and an average coefficient. A first portion of the compressed data structure encodes the differential coefficients for the 2×2 quad of pixels. A second portion of the compressed data structure encodes the average coefficient for the 2×2 quad of pixels. The first portion of the compressed data structure is used to determine signs and exponents differential coefficients which are non-zero. The second portion of the compressed data structure is used to determine a representation of the average coefficient. The result of a weighted sum of the differential coefficients and the average coefficient for the 2×2 quad of pixels is determined using: (i) the determined signs and exponents for the differential coefficients which are non-zero, (ii) the determined representation of the average coefficient, and (iii) respective weights for the differential coefficients. The determined result is used to determine the decoded value. The determined decoded value is outputted.