公开(公告)号：US20090085671A1

公开(公告)日：2009-04-02

申请号：US12236344

申请日：2008-09-23

申请人： David H. Shen ,  James Burnham ,  Ali Tabatabaei ,  Ann P. Shen

发明人： David H. Shen ,  James Burnham ,  Ali Tabatabaei ,  Ann P. Shen

IPC分类号： H03F3/68 ,  H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/193 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/492 ,  H03F2203/45386 ,  H03F2203/45396 ,  H03F2203/45638 ,  H03F2203/7209

摘要： Sharing one or more load inductors comprises receiving a first input signal at a first terminal of a first amplifier and amplifying the first input signal using the first amplifier. The first amplifier is coupled to one or more load inductors at a second terminal of the first amplifier and is coupled to one or more dedicated source inductors at a third terminal of the first amplifier. Also, a second input signal is received at a first terminal of a second amplifier amplifying the second input signal using the second amplifier. The second amplifier is coupled to the one or more load inductors at a second terminal of the second amplifier and is coupled to one or more dedicated source inductors at a third terminal of the second amplifier.

摘要翻译： 共享一个或多个负载电感器包括在第一放大器的第一端接收第一输入信号，并使用第一放大器放大第一输入信号。 第一放大器耦合到第一放大器的第二端处的一个或多个负载电感器，并且耦合到第一放大器的第三端处的一个或多个专用源电感器。 此外，在第二放大器的第一端处接收第二输入信号，该第二放大器使用第二放大器放大第二输入信号。 第二放大器耦合到第二放大器的第二端处的一个或多个负载电感器，并且耦合到第二放大器的第三端处的一个或多个专用源电感器。

公开(公告)号：US20090085545A1

公开(公告)日：2009-04-02

申请号：US12175316

申请日：2008-07-17

申请人： David H. Shen ,  Ann P. Shen

发明人： David H. Shen ,  Ann P. Shen

IPC分类号： G05F1/565

CPC分类号： G05F1/565

摘要： In some implementations, a system includes a low-power voltage regulator that can switch between three power modes: a power shutdown mode, a low power mode, and a higher power mode. The system includes a selector coupled to the voltage regulator to switch between the low power mode and the higher power mode, and a switch to switch between the power shutdown mode and the low or higher power mode. The system also has a control circuit to control the switch and the selector to control operation of the voltage regulator in any of the three power modes. A total current used in the voltage regulator in the low power mode is on the order of microamps or nanoamps. The voltage regulator in the low power mode has two to more orders of magnitude of lower current use than the voltage regulator in the higher power mode.

摘要翻译： 在一些实施方式中，系统包括能够在三种功率模式之间切换的低功率稳压器：电源关闭模式，低功率模式和较高功率模式。 该系统包括耦合到电压调节器以在低功率模式和较高功率模式之间切换的选择器，以及在功率关断模式和低功率或更高功率模式之间切换的开关。 该系统还具有控制电路，用于控制开关和选择器，以控制三种功率模式中的任何一种电压调节器的工作。 在低功率模式下，电压调节器中使用的总电流为微安或纳秒级。 低功耗模式下的电压调节器在较高功率模式下具有比电压调节器低两到几个数量级的低电流使用。

公开(公告)号：US07639092B2

公开(公告)日：2009-12-29

申请号：US11837042

申请日：2007-08-10

申请人： David H. Shen ,  Ann P. Shen

发明人： David H. Shen ,  Ann P. Shen

IPC分类号： H03B5/36

CPC分类号： H03B5/36 ,  H03B2201/025 ,  H03J2200/10

摘要： Embodiments feature techniques and systems for analog and digital tuning of crystal oscillators. In one aspect, some implementations feature a method for tuning a frequency of a crystal oscillator that can include adjusting the tuning frequency of the crystal oscillator from a nominal frequency via a switched-capacitor frequency tuning circuit, the switched-capacitor frequency tuning circuit can have switchable sections to adjust the tuning of the crystal oscillator. The method can include controlling an analog control input that is coupled to a varactor within each of the switchable sections, where each of the switchable sections can include a fixed capacitor in series with the varactor and a switch. The method can involve controlling a digital control input, where the digital control input can electrically connect or disconnect one or more of the switchable sections from the crystal. There can be independent control between the digital and analog tuning mechanisms.

摘要翻译： 实施例用于晶体振荡器的模拟和数字调谐的技术和系统。 一方面，一些实施方式的特征在于一种用于调谐晶体振荡器的频率的方法，该方法可以包括通过开关电容器频率调谐电路从标称频率调整晶体振荡器的调谐频率，开关电容器频率调谐电路可以具有 可切换部分来调节晶体振荡器的调谐。 该方法可以包括控制耦合到每个可切换部分内的变容二极管的模拟控制输入，其中每个可切换部分可以包括与变容二极管串联的固定电容器和开关。 该方法可以涉及控制数字控制输入，其中数字控制输入可以将一个或多个可切换部分与晶体电连接或断开。 数字和模拟调谐机制之间可以独立控制。

公开(公告)号：US20090088121A1

公开(公告)日：2009-04-02

申请号：US12236726

申请日：2008-09-24

申请人： Nianwei Xing ,  David H. Shen ,  Ann P. Shen

发明人： Nianwei Xing ,  David H. Shen ,  Ann P. Shen

IPC分类号： H04B1/18

CPC分类号： H03D7/1441 ,  H03D7/1433 ,  H03D7/1458 ,  H03D7/1483 ,  H03D7/1491 ,  H03D2200/0084

摘要： Circuits and methods for a mixer circuit involve having a first transistor with first and second terminals, where the first terminal is configured to handle an input RF signal. The mixer has a second transistor including a first terminal coupled to the second terminal of the first transistor, a second terminal configured to handle an input oscillator signal, and a third terminal configured to output an intermediate frequency (IF) signal. The IF signal includes a mixed product of the input RF signal and the input oscillator signal. A gate oxide thickness of the first transistor is less than a gate oxide thickness of the second transistor to provide enhanced linearity and a low noise figure. One or more of the mixers can be implemented in a receiver design.

摘要翻译： 用于混频器电路的电路和方法包括具有第一和第二端子的第一晶体管，其中第一端子被配置为处理输入RF信号。 混频器具有第二晶体管，其包括耦合到第一晶体管的第二端子的第一端子，被配置为处理输入振荡器信号的第二端子和被配置为输出中频（IF）信号的第三端子。 IF信号包括输入RF信号和输入振荡器信号的混合积。 第一晶体管的栅极氧化物厚度小于第二晶体管的栅极氧化物厚度，以提供增强的线性度和低噪声系数。 一个或多个混音器可以在接收机设计中实现。

公开(公告)号：US20090088110A1

公开(公告)日：2009-04-02

申请号：US12236888

申请日：2008-09-24

申请人： Axel Schuur ,  Nianwei Xing ,  David H. Shen ,  Chien-Meen Hwang ,  Ann P. Shen ,  Niranjan Talwalkar

发明人： Axel Schuur ,  Nianwei Xing ,  David H. Shen ,  Chien-Meen Hwang ,  Ann P. Shen ,  Niranjan Talwalkar

IPC分类号： H04B1/16

CPC分类号： H04B1/30 ,  H04B1/40 ,  H04B1/525

摘要： A radio frequency receiver includes a passive mixer configured to receive and RF signal and a low input impedance circuit configured to receive the output of the passive mixer.

摘要翻译： 射频接收机包括被配置为接收RF信号的无源混频器和被配置为接收无源混频器的输出的低输入阻抗电路。

公开(公告)号：US20090086806A1

公开(公告)日：2009-04-02

申请号：US12199092

申请日：2008-08-27

申请人： Chien-Meen Hwang ,  Ann P. Shen

发明人： Chien-Meen Hwang ,  Ann P. Shen

IPC分类号： H04L27/01

CPC分类号： H04L25/03006 ,  H04L2025/03535 ,  H04L2025/03745

摘要： In some implementations, a signal is received at a device and a gain change is detected in a component of the device that affects the signal. A state of an equalizer is adjusted in response to the detected gain change to a first state that reduces transient effects introduced into the signal by one or more components in the device as a result of the gain change. The signal is equalized using the equalizer with the state set to the first state and the state of the equalizer is adjusted from the first state to a second state while equalizing the signal using the equalizer such that the second state passes the signal through the equalizer substantially unchanged.

摘要翻译： 在一些实现中，在设备处接收信号，并且在影响信号的设备的部件中检测到增益改变。 调整均衡器的状态以响应于检测到的增益改变为第一状态，其通过增益改变的结果减少由设备中的一个或多个组件引入到信号中的瞬态效应。 使用均衡器将信号均衡，将均衡器的状态设置为第一状态，并且均衡器的状态从第一状态调整到第二状态，同时使用均衡器对信号进行均衡，使得第二状态基本上通过均衡器 不变

公开(公告)号：US20090085622A1

公开(公告)日：2009-04-02

申请号：US12110048

申请日：2008-04-25

申请人： David H. Shen ,  Ann P. Shen ,  Axel Schuur

发明人： David H. Shen ,  Ann P. Shen ,  Axel Schuur

IPC分类号： H03L7/06

CPC分类号： H03L7/183 ,  H03L7/10

摘要： Implementations feature systems and techniques for phase-locked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator.

摘要翻译： 实现功能用于锁相环（PLL）的系统和技术。 在一些方面，实现特征在于具有包括振荡器和可编程参考分频器电路或可编程反馈分频器电路的PLL电路的系统。 PLL包括控制电路，以通过将分频值编程到可编程参考分频器电路和/或可编程反馈分频器电路中来减少PLL建立时间所需的时间，以使振荡器在系统工作频率范围之外操作 在PLL操作启动期间振荡器。 在可变振荡器稳定之后，控制电路可以将另一个分频值编程到可编程参考分频器电路和/或可编程反馈分频器电路中。

公开(公告)号：US20090079497A1

公开(公告)日：2009-03-26

申请号：US12114344

申请日：2008-05-02

申请人： Axel Schuur ,  Ann Shen

发明人： Axel Schuur ,  Ann Shen

IPC分类号： H03B19/12 ,  H03D3/22

CPC分类号： H03D3/009 ,  H03D7/18

摘要： A differential frequency divider includes first and second input terminals each configured to receive a differential input signal. The divider also includes a first output terminal configured to produce a first output signal and a second output terminal configured to produce a second output signal. The divider further includes a third input terminal coupled to the first output terminal and a fourth input terminal coupled to the second output terminal. In addition, the divider includes a first variable current source. Altering a current of the first variable current source causes a change in the phase difference between a first output signal of the first output terminal and a second output signal of the second output terminal.

摘要翻译： 差分分频器包括每个被配置为接收差分输入信号的第一和第二输入端。 分频器还包括被配置为产生第一输出信号的第一输出端和被配置为产生第二输出信号的第二输出端。 分压器还包括耦合到第一输出端的第三输入端和耦合到第二输出端的第四输入端。 此外，分频器包括第一可变电流源。 改变第一可变电流源的电流导致第一输出端的第一输出信号和第二输出端的第二输出信号之间的相位差的改变。

公开(公告)号：US20100329157A1

公开(公告)日：2010-12-30

申请号：US12495064

申请日：2009-06-30

申请人： Nianwei Xing ,  David H. Shen ,  Axel Schuur ,  Ann P. Shen

发明人： Nianwei Xing ,  David H. Shen ,  Axel Schuur ,  Ann P. Shen

IPC分类号： H04B7/005 ,  H03F3/45 ,  G06G7/12

CPC分类号： H03F3/45183 ,  H03F1/3211 ,  H03F2203/45342

摘要： Circuits and methods for a differential circuit involve having one of more pairs of differential transistors with back-gate terminals, where each of the back-gate terminals is biased by a tunable back-gate voltage to compensate for circuit mismatches in the differential circuit and reduce or eliminate even-order harmonics in the output signal. A compensation circuit can be configured to receive data relating to the differential output signal of the differential circuit, and to supply one or more back-gate voltages to the back-gate terminals of the differential transistors to adjust threshold voltages of the differential transistors and suppress even-order harmonics in the differential output signal of the differential circuit.

摘要翻译： 用于差分电路的电路和方法涉及具有多对具有背栅极端子的差分晶体管中的一个，其中每个背栅极端子被可调谐的栅极电压偏置以补偿差分电路中的电路不匹配并且减小 或消除输出信号中的偶次谐波。 补偿电路可以被配置为接收与差分电路的差分输出信号相关的数据，并且向差分晶体管的背栅极端子提供一个或多个反向栅极电压，以调整差分晶体管的阈值电压并抑制 差分电路的差分输出信号中的偶次谐波。

公开(公告)号：US07532079B2

公开(公告)日：2009-05-12

申请号：US11764701

申请日：2007-06-18

申请人： David H. Shen ,  Ann P. Shen

发明人： David H. Shen ,  Ann P. Shen

IPC分类号： H03B5/00

CPC分类号： H03B5/366 ,  H03B2201/0208 ,  H03J2200/10

摘要： Embodiments feature techniques and systems for digitally tuning a crystal oscillator circuit. In one aspect, embodiments feature a method for making a digitally tuned crystal oscillator circuit. The method involves receiving a multi-bit input signal into a digital modulator, modulating the multi-bit input signal with the digital modulator by oversampling or by noiseshaping and oversampling to produce a digitally-modulated output signal having a lower number of bits than the multi-bit input signal. The method also involves coupling a tuning capacitor with the crystal oscillator circuit, and coupling the digitally-modulated output signal from the digital modulator to the crystal oscillator circuit and the tuning capacitor. In some embodiments, the digital modulator can a delta-sigma modulator, a noiseshaping modulator, a delta modulator, a pulse width modulator, a differential modulator, or a continuous-slope delta modulator.

摘要翻译： 实施例用于数字调谐晶体振荡器电路的技术和系统。 在一个方面，实施例的特征在于制造数字调谐晶体振荡器电路的方法。 该方法包括将多位输入信号接收到数字调制器中，通过过采样或通过噪声整形和过采样来调制具有数字调制器的多位输入信号，以产生具有比多数位更低位数的数字调制输出信号 位输入信号。 该方法还涉及将调谐电容器与晶体振荡器电路耦合，并将数字调制输出信号从数字调制器耦合到晶体振荡器电路和调谐电容器。 在一些实施例中，数字调制器可以是Δ-Σ调制器，噪声调制器，Δ调制器，脉冲宽度调制器，差分调制器或连续斜率增量调制器。