公开(公告)号：US5872041A

公开(公告)日：1999-02-16

申请号：US933008

申请日：1997-09-18

Applicant: Ta-Yuan Lee ,  Chi-Hui Lin

Inventor： Ta-Yuan Lee ,  Chi-Hui Lin

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/91

Abstract: A method for fabricating electrodes of a capacitor over a semiconductor substrate is disclosed. The method includes the steps of: forming a base insulating layer over the semiconductor substrate; forming a stacked layer, including an insulating layer and a mask layer, over the base insulating layer; defining the stacked layer to form an opening to the base insulating layer; forming a first conducting layer over the stacked layer; forming a spacer on the sidewall of the first conducting layer in the opening; etching the bottom of the opening by using the mask layer and the spacer as a mask to expose a portion of the semiconductor substrate; forming a second conducting layer in the opening to electrically connect the exposed semiconductor substrate; and removing the spacer to leave the first and the second conducting layers as a capacitor electrode.

Abstract translation: 公开了一种在半导体衬底上制造电容器的电极的方法。 该方法包括以下步骤：在半导体衬底上形成基极绝缘层; 在所述基底绝缘层上形成包括绝缘层和掩模层的层叠层; 限定所述堆叠层以形成到所述基底绝缘层的开口; 在堆叠层上形成第一导电层; 在所述开口中的所述第一导电层的侧壁上形成间隔物; 通过使用掩模层和间隔物作为掩模蚀刻开口的底部以暴露半导体衬底的一部分; 在所述开口中形成第二导电层以电连接所暴露的半导体衬底; 并且移除间隔物以将第一和第二导电层留作电容器电极。

公开(公告)号：US5857127A

公开(公告)日：1999-01-05

申请号：US932622

申请日：1997-09-17

Applicant: Ron-Fu Chu

Inventor： Ron-Fu Chu

IPC: G03F7/30 ,  H01L21/027 ,  G03D5/00

CPC classification number: G03F7/3021

Abstract: An apparatus for use in the photoresist development process of an integrated circuit fabrication is provided to improve the uniformity of development. The apparatus includes: a holder which includes a vertical spindle and a chuck fixed on the top of the vertical spindle, for horizontally holding a semiconductor wafer; a liquid feeder disposed above the holder, for supplying a developer onto the semiconductor wafer; a cup-type housing disposed under the holder, wherein the bottom of the cup-type housing includes a valve for draining the developer and a hole for allowing the vertical spindle to penetrate through; and a hoisting instrument fixed on the bottom of the cup-type housing, so that when the cup-type housing is lifted, the edge of the semiconductor wafer tightly contacts the sidewall of the cup-type housing, thereby forming a dish-like container for containing the developer.

Abstract translation: 提供了用于集成电路制造的光致抗蚀剂显影处理中的装置，以提高显影的均匀性。 该装置包括：保持器，其包括垂直主轴和固定在垂直主轴顶部上的卡盘，用于水平地保持半导体晶片; 设置在所述保持器上方的用于将显影剂供应到所述半导体晶片上的液体进料器; 设置在所述保持器下方的杯型壳体，其中所述杯型壳体的底部包括用于排出所述显影剂的阀和用于允许所述垂直心轴穿过的孔; 以及固定在杯型壳体的底部的起重工具，使得当杯形壳体被提起时，半导体晶片的边缘紧密接触杯形壳体的侧壁，从而形成盘状容器 用于包含开发者。

公开(公告)号：US5966610A

公开(公告)日：1999-10-12

申请号：US2675

申请日：1998-01-05

Applicant: Shiou-Yu Wang ,  Tean-Sen Jen ,  Jia-Shyong Cheng

Inventor： Shiou-Yu Wang ,  Tean-Sen Jen ,  Jia-Shyong Cheng

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC classification number: H01L28/92 ,  H01L28/91 ,  H01L27/10814 ,  H01L27/10852

Abstract: A method of fabricating a capacitor plate constitutes first providing a substrate. Then, first insulating layer is formed over the substrate. Sequentially, a buffering layer and a second insulating layer, both of which constitute a stacked structure, are formed over the first insulating layer. Next, the stacked structure is patterned into an opening thereby exposing a portion of the first insulating layer therethrough. Subsequently, conducting spacers are formed on the sidewalls of the opening. The second insulating layer is thereafter removed, and simultaneously a portion of the first insulating layer not covered by the buffering layer and the conducting spacers are removed to form a contact window, thereby exposing a portion of the substrate therethrough. Then, a conducting layer is conformably deposited over the substrate, and thereafter etched away until a portion of the buffering layer is exposed. Finally, the exposed buffering layer is removed. The remaining conducting layer and the conducting spacers constitute the capacitor's bottom electrode plate.

Abstract translation: 构成电容器板的方法首先构成基板。 然后，在基板上形成第一绝缘层。 顺序地，在第一绝缘层上形成缓冲层和构成堆叠结构的第二绝缘层。 接下来，将堆叠结构图案化成开口，从而使第一绝缘层的一部分暴露于其中。 随后，在开口的侧壁上形成导电间隔物。 此后除去第二绝缘层，同时将不被缓冲层和导电间隔物覆盖的第一绝缘层的一部分移除以形成接触窗，从而使基板的一部分暴露。 然后，将导电层顺应地沉积在衬底上，然后蚀刻掉直到缓冲层的一部分露出。 最后，暴露的缓冲层被去除。 剩余的导电层和导电间隔物构成电容器的底部电极板。

公开(公告)号：US5955757A

公开(公告)日：1999-09-21

申请号：US54547

申请日：1998-04-03

Applicant: Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng

Inventor： Tean-Sen Jen ,  Shiou-Yu Wang ,  Jia-Shyong Cheng

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10808 ,  Y10S257/904 ,  Y10S257/906

Abstract: The present invention discloses a DRAM structure with multiple memory cells sharing the same bit-line contact. The DRAM structure of the present invention comprises: a substrate; an active region formed on the substrate, with a center region and a plurality of protrusion regions connecting to the two sides of the center region; a plurality of word-lines, disconnected from each other, each crossing the corresponding protrusion region; a plurality of channel regions, formed where the protrusion region overlaps with the word-lines; a plurality of source regions, formed at the outer areas of the channel regions; a sharing drain region, formed at the center region of the active region; a bit-line contact, formed on surface of the sharing drain region; a bit-line, crossing the center region and electrically connected to the sharing drain region via the bit-line contact; a plurality of capacitors, electrically connected to the source regions; and a plurality of metal lines, electrically connected to the corresponding word-lines.

Abstract translation: 本发明公开了具有共享相同位线接触的多个存储单元的DRAM结构。 本发明的DRAM结构包括：基板; 形成在所述基板上的有源区域，具有连接到所述中心区域的两侧的中心区域和多个突出区域; 多个字线彼此断开，每个字线与相应的突出区域交叉; 多个通道区域，形成在突起区域与字线重叠的位置上; 多个源区，形成在沟道区的外部区域; 形成在有源区的中心区域的共用漏极区; 形成在共享漏极区域的表面上的位线接触; 位线，穿过中心区域并且经由位线接触电连接到共享漏极区域; 多个电容器，电连接到源极区域; 和多个金属线，电连接到相应的字线。