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126 条记录 (耗时 0.029 秒)

    Bandwidth weighting mechanism based network-on-chip (NoC) configuration
    1.
    发明授权
    Bandwidth weighting mechanism based network-on-chip (NoC) configuration 有权

    公开(公告)号：US10983910B2

    公开(公告)日：2021-04-20

    申请号：US16258440

    申请日：2019-01-25

    申请人： NetSpeed Systems, Inc.

    发明人： Joseph Rowlands ,  Joji Philip

    IPC分类号： G06F12/0813 ,  G06F12/0811 ,  H04L12/725 ,  H04L12/773 ,  G06F9/38 ,  H04L12/713

    摘要： The present disclosure relates to a bandwidth weighting mechanism based NoC configuration/constructions for packet routing. In an aspect, the present disclosure relates to a method for packet routing in a circuit architecture, wherein the method includes the steps of managing, at a router of the circuit architecture, one or more catch-up bits, each of the one or more catch-up bits indicating that the router has reset a round of round-robin based packet routing without allowing an agent corresponding to the each of the one or more catch-up bits to complete its respective round; and allowing, by the router, the agent to continue its respective round in catch-up state such that upon completion of the respective round, the agent is switched to normal state.

    Generating physically aware network-on-chip design from a physical system-on-chip specification
    2.
    发明授权
    Generating physically aware network-on-chip design from a physical system-on-chip specification 有权

    公开(公告)号：US10218580B2

    公开(公告)日：2019-02-26

    申请号：US14743865

    申请日：2015-06-18

    申请人： NetSpeed Systems

    发明人： Rajesh Chopra ,  Yang-Trung Lin ,  Sailesh Kumar

    IPC分类号： H04L12/24 ,  H04L12/933

    摘要： Different example implementations of the present disclosure relates to methods and computer readable mediums for automatically generating physically aware NoC design and physically aware NoC Specification based on one or more of given SoC architectural details, physical information of SoC, traffic specification, power profile and one or more constraints. The method includes steps of receiving input information, determining the location/position of different NoC agents, interconnecting channels, pins, I/O interfaces, physical/virtual boundaries, number of layers, size/depth/width of different channels at different time, and locating/configuring the different NoC agents, interconnecting channels, pins, I/O interfaces, and physical/virtual boundaries.

    Buffer Sizing of a NoC Through Machine Learning
    3.
    发明申请
    Buffer Sizing of a NoC Through Machine Learning 审中-公开

    公开(公告)号：US20180324113A1

    公开(公告)日：2018-11-08

    申请号：US16037924

    申请日：2018-07-17

    申请人： NetSpeed Systems, Inc.

    发明人： Eric NORIGE ,  Nishant RAO ,  Sailesh KUMAR

    IPC分类号： H04L12/861 ,  H04L12/24

    CPC分类号： H04L49/9005 ,  H04L41/14 ,  H04L41/145 ,  H04L43/0864 ,  H04L43/0894 ,  H04L43/16 ,  H04L49/109 ,  H04L49/30

    摘要： The present disclosure is directed to buffer sizing of NoC link buffers by utilizing incremental dynamic optimization and machine learning. A method for configuring buffer depths associated with one or more network on chip (NoC) is disclosed. The method includes deriving characteristics of buffers associated with the one or more NoC, determining first buffer depths of the buffers based on the characteristics derived, obtaining traces based on the characteristics derived, measuring trace skews based on the traces obtained, determining second buffer depths based on the trace skews measured, optimizing the buffer depths associated with the network on chip (NoC) based on the second buffer depths, and configuring the buffer depths associated with one or more network on chip (NoC) based on the buffer depths optimized.

    Automatic generation of power management sequence in a SoC or NoC
    4.
    发明授权
    Automatic generation of power management sequence in a SoC or NoC 有权

    公开(公告)号：US10042404B2

    公开(公告)日：2018-08-07

    申请号：US14498907

    申请日：2014-09-26

    申请人： NetSpeed Systems

    发明人： Anup Gangwar ,  Vishnu Mohan Pusuluri ,  Poonacha Kongetira ,  Sailesh Kumar

    IPC分类号： G06F17/50 ,  G06F1/26

    摘要： Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.

    Transaction expansion for NoC simulation and NoC design
    5.
    发明授权
    Transaction expansion for NoC simulation and NoC design 有权

    公开(公告)号：US09928204B2

    公开(公告)日：2018-03-27

    申请号：US14620642

    申请日：2015-02-12

    申请人： NetSpeed Systems

    发明人： Eric Norige ,  Sailesh Kumar

    IPC分类号： G06F13/12 ,  G06F13/42 ,  H04L12/721

    CPC分类号： G06F13/4221 ,  H04L45/40

    摘要： Methods and example implementations described herein are generally directed to interconnect architecture, and more specifically, to generation of one or more expanded transactions for conducting simulations and/or NoC design. Aspects of the present disclosure include processing of input traffic specification that is given in terms of groups of hosts, requests, and responses to the requests, in order to generate one or more appropriate/correct expanded transactions that can be simulated.

    Automatic buffer sizing for optimal network-on-chip design
    6.
    发明授权
    Automatic buffer sizing for optimal network-on-chip design 有权

    公开(公告)号：US09860197B2

    公开(公告)日：2018-01-02

    申请号：US15438674

    申请日：2017-02-21

    申请人： NetSpeed Systems, Inc.

    发明人： Sailesh Kumar

    IPC分类号： H04L12/28 ,  H04L12/861 ,  H04L12/933 ,  H04L12/26 ,  H04L12/841

    CPC分类号： H04L49/9005 ,  H04L41/12 ,  H04L43/0888 ,  H04L43/0894 ,  H04L45/586 ,  H04L47/283 ,  H04L49/109

    摘要： The present disclosure relates to automatic sizing of NoC channel buffers of one or more virtual channels to optimize NoC design, SoC design, and to meet defined performance objectives. The present disclosure further relates to a NoC element such as a router or a bridge having input ports associated with input virtual channels, and output ports associated with output virtual channels, wherein, aspects of the present disclosure enable sizing of any or a combination of the width of the input virtual channel(s), width of the output virtual channel(s), buffer(s) associated with input virtual channels, and buffer(s) associated with output virtual channels. In another aspect, the sizing can be performed based on one or a combination of defined performance objectives, throughputs of the input virtual channels, and throughputs of the output virtual channels, load characteristics, bandwidth characteristics of each input/output channel, among other like parameters.

    Hierarchical asymmetric mesh with virtual routers
    8.
    发明授权
    Hierarchical asymmetric mesh with virtual routers 有权

    公开(公告)号：US09774498B2

    公开(公告)日：2017-09-26

    申请号：US14750096

    申请日：2015-06-25

    申请人： NetSpeed Systems

    发明人： Sailesh Kumar ,  Eric Norige ,  Joji Philip ,  Mahmud Hassan ,  Sundari Mitra ,  Joseph Rowlands

    IPC分类号： H04L12/715 ,  H04L12/24 ,  H04L12/775

    CPC分类号： H04L41/0803 ,  G06F15/7825 ,  H04L45/04 ,  H04L45/58

    摘要： A network-on-chip configuration includes a first plurality of cores arranged in a two-dimensional mesh; a first plurality of routers, each of the first plurality of routers associated with a corresponding local one of the first plurality of cores, each of the first plurality of routers having a plurality of directional ports configured to provide connections to other ones of the first plurality of routers; a second plurality of cores disposed around a periphery of the two-dimensional mesh arrangement; and a second plurality of routers, each of the second plurality of routers associated with a corresponding local one of the second plurality of cores, and having a directional port configured to provide a connection to a neighboring one of the first plurality of routers.