Automatic generation of power management sequence in a SoC or NoC

    公开(公告)号:US10042404B2

    公开(公告)日:2018-08-07

    申请号:US14498907

    申请日:2014-09-26

    申请人: NetSpeed Systems

    IPC分类号: G06F17/50 G06F1/26

    摘要: Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.

    AUTOMATIC GENERATION OF POWER MANAGEMENT SEQUENCE IN A SOC OR NOC
    5.
    发明申请
    AUTOMATIC GENERATION OF POWER MANAGEMENT SEQUENCE IN A SOC OR NOC 审中-公开
    自动生成SOC或NOC中的电源管理序列

    公开(公告)号:US20170060204A1

    公开(公告)日:2017-03-02

    申请号:US14498907

    申请日:2014-09-26

    申请人: NetSpeed Systems

    IPC分类号: G06F1/26

    摘要: Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.

    摘要翻译: 本公开的系统和方法涉及从具有NoC设计规范,业务规范,业务简档,功率简档信息的一个或组合的给定输入规范自动和/或动态地生成用于SoC和NoC架构的一个或多个功率管理序列 ,发起者 - 消费者关系,组件之间的相互依赖性,保留信息,外部因素以及其他联盟配置/信息,以实现一个或多个硬件元件从一个功率配置文件到另一个功率配置文件的高效切换。

    CLOCK GATING FOR SYSTEM-ON-CHIP ELEMENTS
    7.
    发明申请
    CLOCK GATING FOR SYSTEM-ON-CHIP ELEMENTS 有权
    系统片上元素的时钟增益

    公开(公告)号:US20170063618A1

    公开(公告)日:2017-03-02

    申请号:US14504291

    申请日:2014-10-01

    申请人: NetSpeed Systems

    摘要: An aspect of the present disclosure provides a hardware element in a Network on Chip (NoC), wherein the hardware element includes a clock gating circuit configures one or more neighboring hardware elements to activate before receiving new incoming data and to sleep after a defined number of cycles, wherein the defined number of cycles can be counted from a cycle having non-receipt of incoming data and/or having a clearance of all data within an input queue of a source hardware element.

    摘要翻译: 本公开的一个方面提供了一种片上网络(NoC)中​​的硬件元件,其中所述硬件元件包括时钟门控电路,在接收新的输入数据之前配置一个或多个相邻的硬件元件以激活,并且在定义数量的 周期,其中可以从没有接收到输入数据的周期和/或具有源硬件元件的输入队列内的所有数据的间隔来计数定义的周期数。

    Clock gating for system-on-chip elements
    10.
    发明授权
    Clock gating for system-on-chip elements 有权
    时钟门控系统级芯片元件

    公开(公告)号:US09571341B1

    公开(公告)日:2017-02-14

    申请号:US14504291

    申请日:2014-10-01

    申请人: NetSpeed Systems

    摘要: An aspect of the present disclosure provides a hardware element in a Network on Chip (NoC), wherein the hardware element includes a clock gating circuit configures one or more neighboring hardware elements to activate before receiving new incoming data and to sleep after a defined number of cycles, wherein the defined number of cycles can be counted from a cycle having non-receipt of incoming data and/or having a clearance of all data within an input queue of a source hardware element.

    摘要翻译: 本公开的一个方面提供了一种片上网络(NoC)中​​的硬件元件,其中所述硬件元件包括时钟门控电路,在接收新的输入数据之前配置一个或多个相邻硬件元件以激活,并且在定义数量的 周期,其中可以从没有接收到输入数据的周期和/或具有源硬件元件的输入队列内的所有数据的间隔来计数定义的周期数。