摘要:
A differential amplifier circuit at the input stage is configured with a twin differential type having a first differential amplifier circuit (11) and a second differential amplifier circuit (12), respective outputs of which are received by a first and a second source-grounded amplifier (M5, M10). The second source-grounded amplifier (M10) is connected to a current mirror circuit (M11, M12), which is driven by the drain current of the second source-grounded amplifier (M10). With this configuration, the dynamic range for the upper half portion of an alternating signal output from an output terminal (OUT) is determined by the current supply capability of the first source-grounded amplifier (M5) and the dynamic range for the lower half portion is determined by the current supply capability of the second source-grounded amplifier (M10). This eliminates the need of a constant current circuit of a large current for generating a signal having lower half portion in which the waveform distortion is improved.
摘要:
By A/D converting a signal output from a mixer (4) and inputting the A/D converted signal to a DSP (8), and generating AGC control data (DL) corresponding to a level of the signal to control a gain of an LNA (3) in such a manner that a voltage input to an A/D converting circuit (7) is lower than a full scale voltage of the A/D converting circuit (7), it is possible to prevent a signal having an excessively high level beyond a dynamic range of the A/D converting circuit (7) from being input to the A/D converting circuit (7). By controlling the gain of the LNA (3) corresponding to a level of a broad band signal before passing through a BPF (11) and controlling a gain of an IF amplifier (12) corresponding to a level of a narrow band signal after passing through the BPF (11), moreover, it is possible to properly control a gain of an AGC as a whole in consideration of signal levels of both a desirable wave and a disturbing wave.
摘要:
An FM transmitter improved in degree of freedom of selecting components. The FM transmitter comprises an oscillator 72 connected to a crystal oscillator 70, a clock generating circuit 50 for generating a clock signal having a frequency which is an integral multiple of the frequency of the output signal from the oscillator 72 by using the output signal as a reference frequency signal fr1, a DSP 20 operable synchronously with the clock signal and adapted for conducting digital stereo modulation, digital FM modulation, and digital IQ modulation of inputted stereo data, a frequency synthesizer 60 for generating a signal having a frequency which is an integral multiple of the frequency of the output signal from the oscillator 72 by using the output signal as a reference frequency signal fr2, mixers 40, 42 for mixing the signals outputted from the DSP 20 with the signal generated by the frequency synthesizer 60, an adder 44 for adding the outputs from the mixers 40, 42, and amplifier 46 for amplifying the output signal from the adder 44 to transmit it from an antenna 48.
摘要:
An idling current setting circuit (3) includes: current setting transistors (Q3, Q4) connected to output transistors (Q1, Q2) in a driver (2) in current mirror form; a plurality of current setting resistors (R1 to R4); and a plurality of switches (ASW1 to ASW4) for switching to any of the current setting resistors (R1 to R4). This enables the idling current to be set by the current mirror ratio between the current setting transistors (Q3, Q4) having no connection with the open gain of the power amplifier and the output transistors (Q1, Q2), so that the idling current can be arbitrarily set independently of the open gain.
摘要:
A clock generating circuit having a simple constitution and an audio system are disclosed.The clock generating circuit (300) comprises an oscillator (12) for generating a reference frequency signal by means of a crystal oscillator (10) of a resonance frequency of 32.768 kHz, a PLL circuit for generating a signal synchronizing with the reference frequency signal generated by the oscillator (12) and having a frequency which is M times the reference frequency signal, a first frequency divider (30) for generating a first clock signal (CLK1) having a frequency of 32 kHz by frequency-dividing the signal generated by the PLL circuit at a division ratio N1, a second frequency divider (32) for generating a second clock signal (CLK2) having a frequency of 38 kHz by frequency-dividing the signal generated by the PLL circuit at a division ratio N2, and a third frequency divider (34) for generating a third clock signal (CLK3) having a frequency of 48 kHz by frequency-dividing the signal generated by the PLL circuit at a division ratio N3.
摘要:
A received signal level is detected in each of a wide band, middle band, and narrow band and each detected signal is converted to a digital signal. A DSP 18 determines the enabled/disabled state of an LNA 3 and an attenuator 4 as well as a gain adjustment amount based on the signal level of each band. For example, the gain adjustment is not performed when the signal level of the narrow band including a desired frequency is not larger than a prescribed value even the signal level of the wide band or middle band is larger than a prescribed value. When the signal level of the narrow band is larger than the prescribed value exceeding a gain adjustable limit level in the attenuator 4, the gain of the LNA 3 is adjusted, while maintaining the gain adjustable amount in the attenuator 4 around the limit level, to reduce the gain as a whole.
摘要:
There are provided a frequency converting circuit 21 for inputting a broadband IF signal which includes a disturbing wave and carrying out a frequency conversion with an oscillating signal having a frequency of a desirable wave, and outputting a signal including a sum frequency component of a frequency component of a disturbing wave which is included in the IF signal and a frequency component of a desirable wave of the oscillating signal and a difference frequency component therebetween, and a low-pass filter 22 for attenuating the sum frequency component to output a signal of the difference frequency component, and a presence of an intermodulation disturbance is detected based on a frequency relationship between two difference frequency components output from the low-pass filter 22. Consequently, it is possible to easily detect the intermodulation disturbance irrespective of a level of a received signal or a desirable wave included therein without carrying out a processing for amplitude modulating the received signal.
摘要:
The present invention provides a variable gain amplifier including a plurality of initial-stage LNAs 1 to 4 connected parallel to one input terminal IN, a next-stage LNA 5 connected after the initial-stage LNAs 1 to 4 and a variable current source 20 that performs control such that a total value of initial-stage control currents IB1 to IB4 simultaneously flowing through the initial-stage LNAs 1 to 4 is kept constant and such that-next-stage control currents IB13 and IB24 of magnitude proportional to the initial-stage control currents IB1 to IB4 which are let flow through the initial-stage LNAs 1 to 4 are let flow through the next-stage LNA 5, wherein the necessity for causing an excessively large fixed current to flow through the next-stage LNA 5 is eliminated and the next-stage control currents IB13 and IB24 are reduced to a minimum necessary magnitude so that increases of useless current consumption can be suppressed.
摘要:
An object of the present invention is to provide a receiver, a digital-analog converter and a tuning circuit in which temperature compensating components can be formed on a semiconductor substrate while reducing component costs. An FM receiver 100 is constituted by including an antenna 1, a high frequency receiving circuit 2, a local oscillator 3, two digital-analog converters (DACs) 4, 6, a control section 8, a mixing circuit 9, an intermediate frequency amplification circuit 10, a detection circuit 11, a low frequency amplification circuit 12 and the speaker 13. The DACs 4, 6 have a predetermined temperature coefficient, of which output voltage is changed in accordance with ambient temperature. When a characteristic of VCO 31 is changed with variations of ambient temperature so as to cause a control voltage applied to the VCO 31 to be changed, output voltages of the DACs 4, 6 are also changed similarly.
摘要:
An oscillator capable of reducing a noise component when partly formed by using the CMOS process or the MOS process. A high-frequency amplifier circuit, a mixing circuit, a local oscillator 13, intermediate-frequency filters, an intermediate-frequency amplifier circuit, a limit circuit, an FM detection circuit, and a stereo demodulation circuit which constitute an FM receiver are formed as a one-chip component. The local oscillator 13 is formed on a semiconductor substrate by using the CMOS process or the MOS process and the transistors constituting the circuit are p-channel type FETs 21, 22. Moreover, the local oscillator 13 has a resonance circuit whose one end is connected to a DC bias circuit composed of a resistor 27 and the center voltage of the oscillation is set to a value higher than 0 V.