公开(公告)号：US20110302541A1

公开(公告)日：2011-12-08

申请号：US12977376

申请日：2010-12-23

申请人： Kai Yang ,  Michael Lyons ,  Kuo-Ching Lin ,  Wei-Ting Tu ,  Chih-Wen Chang ,  Tein-Chun Wei

发明人： Kai Yang ,  Michael Lyons ,  Kuo-Ching Lin ,  Wei-Ting Tu ,  Chih-Wen Chang ,  Tein-Chun Wei

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/504 ,  G06F2217/10

摘要： Methods and systems for evaluating checker quality of a verification environment are provided. In some embodiments, an overall sensitivity for the verification environment and an individual sensitivity for a respective checker are calculated. The overall sensitivity is a probability that a plurality of problematic design behaviors, which are propagated to a checker system including at least one checker, can be detected by the verification environment. The individual sensitivity is a probability that a plurality of problematic design behaviors, which are propagated to at least one specific probe among a plurality of probes of a design, can be detected by the checker corresponding to the specific probe. The overall checker sensitivity numbers can show the robustness of the check system. The individual checker sensitivity can guide the user which individual checker or checkers to improve.

摘要翻译： 提供了用于评估验证环境的检查器质量的方法和系统。 在一些实施例中，计算验证环境的总体灵敏度和相应检查器的个体灵敏度。 总体灵敏度是通过验证环境可以检测到传播到包括至少一个检验器的检查系统的多个有问题的设计行为的概率。 个体敏感度是通过与特定探针对应的检查器可以检测到在设计的多个探针中传播到至少一个特定探针的多个有问题的设计行为的概率。 整体检查灵敏度数字可以显示检查系统的稳健性。 单独的检查灵敏度可以指导用户哪个单独的检查器或检查器改进。

公开(公告)号：US07970597B2

公开(公告)日：2011-06-28

申请号：US12120895

申请日：2008-05-15

申请人： Meng-Chyi Lin ,  Fei-Sheng Hsu ,  Sweyyan Shei

发明人： Meng-Chyi Lin ,  Fei-Sheng Hsu ,  Sweyyan Shei

IPC分类号： G06F9/455

CPC分类号： G06F17/5027 ,  G06F11/261

摘要： A circuit emulator includes emulation resources programmed to emulate a circuit, a clocking system for clocking logic implemented by the emulation resources, a resource interface circuit, a logic analyzer, and a debugger. The resource interface circuit supplies input signals to the emulation resources, stores data representing behavior of signals generated by the emulation resources produces in response to the input signals and configures operating characteristics of the clocking system. Upon detecting a specified event in the selected signals of the emulation resources, the logic analyzer asserts a trigger signal telling the clocking system to stop clocking the emulation resources. Communicating with the resource interface circuit and the logic analyzer via a packet routing network, the debugger acquires and processes the data stored by the resource interface circuit and transmits commands to the resource interface circuit and the logic analyzer specifying clocking system operating characteristics, controlling signal data transfer to the debugger, and defining the signal events the logic analyzer is to detect.

摘要翻译： 电路仿真器包括被编程为仿真电路的仿真资源，用于由仿真资源实现的时钟逻辑的时钟系统，资源接口电路，逻辑分析器和调试器。 资源接口电路向仿真资源提供输入信号，存储表示响应于输入信号产生的仿真资源产生的信号的行为的数据，并配置计时系统的操作特性。 在检测到所选择的仿真资源信号中的指定事件时，逻辑分析器断言触发信号，告诉时钟系统停止对仿真资源的计时。 通过分组路由网络与资源接口电路和逻辑分析仪进行通信，调试器获取并处理资源接口电路存储的数据，并向资源接口电路和逻辑分析仪发送命令，指定时钟系统的运行特性，控制信号数据 传输到调试器，并定义逻辑分析仪要检测的信号事件。

公开(公告)号：US07739646B2

公开(公告)日：2010-06-15

申请号：US11839042

申请日：2007-08-15

申请人： Po-Hung Lin ,  Ho-Che Yu ,  Tian-Hau Tsai ,  Shyh-Chang Lin ,  Shi-Hong Bai

发明人： Po-Hung Lin ,  Ho-Che Yu ,  Tian-Hau Tsai ,  Shyh-Chang Lin ,  Shi-Hong Bai

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5077

摘要： A computer-based placement and routing (P&R) tool stores a set of circuit patterns, each describing a separate device group by referencing each device of the device group and by indicating which device elements forming the referenced devices are interconnected by nets, a set of placement patterns, each providing a guide for placing IC device elements forming a device group described by a corresponding one of the circuit patterns and a set of routing styles to act as guides for routing nets between device elements placed in particular patterns. To produce a layout for an analog IC described by a netlist, the P&R tool identifies each set of devices in the IC forming a device group described by any of the circuit patterns. The P&R tool then generates a separate device group layout for each identified device group using the placement patterns as guides for placing device elements within the device group layout and using the routing styles as guides for routing nets interconnecting device elements within the device group layout. The P&R tool also generates a layout for each device not included in any identified device group. The tool then generates a layout for the IC incorporating each generated device and device group layout.

摘要翻译： 基于计算机的放置和布线（P＆R）工具存储一组电路图案，每个电路图案通过参考设备组的每个设备并通过指示通过网络将形成被引用设备的设备元件相互连接来描述单独的设备组，一组 布置图案，每个提供用于放置形成由对应的一个电路图案描述的设备组的IC设备元件和一组路由样式的引导件，以用作在放置在特定图案中的设备元件之间布线网络的引导。 为了产生由网表描述的模拟IC的布局，P＆R工具识别IC中的每组设备，形成由任何电路图形描述的设备组。 然后，P＆R工具为每个识别的设备组生成单独的设备组布局，使用放置模式作为在设备组布局中放置设备元素的引导，并使用路由样式作为在设备组布局中互连设备元素的路由网络的引导。 P＆R工具还为未包含在任何识别的设备组中的每个设备生成布局。 然后，该工具生成包含每个生成的设备和设备组布局的IC的布局。

公开(公告)号：US07178123B2

公开(公告)日：2007-02-13

申请号：US10975151

申请日：2004-10-27

申请人： Po-Hung Lin ,  Shyh-Chang Lin

发明人： Po-Hung Lin ,  Shyh-Chang Lin

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F2217/74

摘要： A system for processing a netlist description of a circuit to generate a display of a schematic diagram including representations of cells and nets first determines positions of the cell instance representations within the schematic diagram and then displays the schematic diagram, including the cell instance representations but no representations of the nets. When a user requests a zoom in operation to display a smaller portion of the schematic diagram at a scale at which net representations can be viewed, the system determines routes for representations of nets that are to reside in that portion of the schematic diagram and then displays those net representations upon zooming in to that portion of the schematic diagram. When the user requests a pan operation to shift the display to another portion of the schematic diagram, the system determines routes for representations of nets that are to reside in that other portion of the schematic diagram and then displays those net representations upon panning to that other portion of the schematic diagram.

摘要翻译： 用于处理电路的网表描述的系统以生成包括单元和网的表示的示意图的显示，首先确定示意图中单元实例表示的位置，然后显示示意图，包括单元实例表示但不包括 网的表示。 当用户请求放大操作以便以可以查看网络表示的比例显示原理图的较小部分时，系统确定要驻留在原理图的该部分中的网络的表示的路由，然后显示 放大到原理图的那部分时的这些净表示。 当用户请求平移操作将显示器移动到原理图的另一部分时，系统确定要驻留在原理图的其他部分的网络的表示的路由，然后在平移到另一个网络时显示这些网络表示 部分原理图。

公开(公告)号：US07178114B2

公开(公告)日：2007-02-13

申请号：US10863122

申请日：2004-06-07

申请人： Chia-Chi Lin ,  Ju-Chian Wang ,  Min-Wen Chang

发明人： Chia-Chi Lin ,  Ju-Chian Wang ,  Min-Wen Chang

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A computer-aided design tool for automatically generating a layout for an electronic device to be formed by a set of objects implemented within an integrated circuit, receives input from a user defining a device template specifying shapes, dimensions and relative positions within the layout of the objects forming the device. Some of the object dimensions and/or relative positions are specified as functions of values of input parameters to be supplied by the user. When the user supplies the input parameters, the CAD tool evaluates the functions to determine the object dimensions and/or positions that are functions of the input parameters and then generates a layout for the electronic device wherein object shapes, dimensions and relative positions are as specified in the device template and consistent with the function evaluations. The device template may also include instructions for modifying the layout, for example, indicating that copies of an object are to form an array in the layout, that copies of one object are to fill another object, that an object is to be added to the layout having a shape that is a Boolean function of other objects, and that objects are to be added to or removed from the layout.

摘要翻译： 一种用于自动生成由集成电路中实现的一组对象形成的电子设备的布局的计算机辅助设计工具，从用户接收定义设备模板的输入，该设备模板指定在该布局内的形状，尺寸和相对位置 形成装置的物体。 一些对象尺寸和/或相对位置被指定为由用户提供的输入参数的值的函数。 当用户提供输入参数时，CAD工具评估函数以确定作为输入参数的函数的对象尺寸和/或位置，然后生成电子设备的布局，其中对象形状，尺寸和相对位置如指定 在设备模板中并与功能评估一致。 设备模板还可以包括用于修改布局的指令，例如，指示对象的副本要在布局中形成数组，一个对象的副本要填充另一个对象，即将对象添加到 布局的形状是其他对象的布尔函数，并且对象将被添加到布局或从布局中移除。

公开(公告)号：US07013457B2

公开(公告)日：2006-03-14

申请号：US09682140

申请日：2001-07-26

申请人： Tai-Ying Chiang ,  Jing-Yang Jou ,  Ming-Chih Lai ,  Jien-Shen Tsai

发明人： Tai-Ying Chiang ,  Jing-Yang Jou ,  Ming-Chih Lai ,  Jien-Shen Tsai

IPC分类号： G06F9/44

CPC分类号： G06F11/362

摘要： A computer system has an input system and an output system. Program code to be debugged has a plurality of program code statements. The input system is utilized to indicate an error variable in the program code. The error variable has an error value that differs from a desired value. An error set of the error variable is obtained, which is a subset of the statements in the computer readable code. Each statement in the error set is relationally connected to the error variable. A priority value is given to each statement in the error set. The priority values indicate a computed probability that the associated statement is an error source of the error variable. Finally, the output system is used to present each statement in the error set in an ordered manner according to the priority values.

摘要翻译： 计算机系统具有输入系统和输出系统。 要调试的程序代码具有多个程序代码语句。 输入系统用于指示程序代码中的错误变量。 错误变量的值与所需值不同。 获得错误变量的错误集，这是计算机可读代码中的语句的一个子集。 错误集中的每个语句都与错误变量相关联。 给出错误集中的每个语句的优先级值。 优先级值表示计算出的关联语句是错误变量的错误源的概率。 最后，输出系统用于根据优先级值以有序的方式向错误集中呈现每个语句。

公开(公告)号：US06920620B2

公开(公告)日：2005-07-19

申请号：US10160690

申请日：2002-05-31

申请人： Hung-Lin Hsiao ,  Jui-Chien Wang

发明人： Hung-Lin Hsiao ,  Jui-Chien Wang

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5081

摘要： In a computer-implemented method and system for creating a test component layout, after creating a reference component layout that is composed of a set of polygonal working shapes, a plurality of shape parameters are defined for the working shapes of the reference component layout, and a parameter template is formed based on the shape parameters of the reference component layout. Thereafter, user-defined distance values corresponding to the shape parameters may be inputted into the parameter template, and the test component layout is automatically created by adjusting geometry of the working shapes of the reference component layout with reference to the user-defined distance values inputted into the parameter template.

摘要翻译： 在用于创建测试组件布局的计算机实现的方法和系统中，在创建由一组多边形工作形状组成的参考组件布局之后，为参考组件布局的工作形状定义多个形状参数，以及 基于参考组件布局的形状参数形成参数模板。 此后，可以将与形状参数相对应的用户定义的距离值输入到参数模板中，并且参考输入的用户定义的距离值来调整参考组件布局的工作形状的几何形状来自动创建测试组件布局 进入参数模板。

公开(公告)号：US20130055177A1

公开(公告)日：2013-02-28

申请号：US13596069

申请日：2012-08-28

申请人： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

发明人： Hung Chun Chiu ,  Meng-Chyi Lin ,  Kuen-Yang Tsai ,  Sweyyan Shei ,  Hwa Mao ,  Yingtsai Chang

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F2217/14

摘要： User's RTL design is analyzed and instrumented so that signals of interest are preserved and can be located in the net list after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the net list to ensure that signal values can be accessed at runtime. After that, a P&R process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations in FPGAs. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

摘要翻译： 对用户的RTL设计进行分析和检测，以便保留感兴趣的信号，并在合成后将其置于网络列表中。 然后，执行用户的RTL合成和设计分区的原始流程。 分析输出以定位感兴趣的信号。 锁存器有选择地插入到网络列表中，以确保在运行时可以访问信号值。 之后，执行P＆R处理，并分析输出以将信号名称与FPGA中的寄存器（触发器和锁存器）或存储器块位置相关联。 建立并保存关联数据库以供运行时使用。 在运行期间，可以在工作站上提供软件组件，供用户查询与RTL分层信号名称对应的信号值。

公开(公告)号：US20130047134A1

公开(公告)日：2013-02-21

申请号：US13443523

申请日：2012-04-10

申请人： Chih-Neng HSU ,  I-Liang LING ,  Qi GUO

发明人： Chih-Neng HSU ,  I-Liang LING ,  Qi GUO

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Methods and systems for viewing and debugging HDL designs having SystemVerilog interface constructs are provided. An HDL design code is received, wherein the design code comprises a first module, a second module and a SystemVerilog interface construct. A first object corresponding to the first module, a second object corresponding to the second module and an interface object corresponding to the interface construct are displayed in a schematic view. The interface object is disposed between the first and second objects, and a shape of the interface object is different from that of the first and second objects. The interface signals from the first object to the second object and the interface signals from the second object to the first object pass through the interface object.

摘要翻译： 提供了用于查看和调试具有SystemVerilog接口结构的HDL设计的方法和系统。 接收HDL设计代码，其中设计代码包括第一模块，第二模块和SystemVerilog接口结构。 对应于第一模块的第一对象，对应于第二模块的第二对象和对应于接口结构的接口对象以示意图的方式显示。 接口对象设置在第一和第二对象之间，并且接口对象的形状与第一和第二对象的形状不同。 接口信号从第一个对象到第二个对象，从第二个对象到第一个对象的接口信号通过接口对象。

公开(公告)号：US08336001B2

公开(公告)日：2012-12-18

申请号：US12913674

申请日：2010-10-27

申请人： Fong-Yuan Chang ,  Wai-Kei Mak ,  Ren-Song Tsay

发明人： Fong-Yuan Chang ,  Wai-Kei Mak ,  Ren-Song Tsay

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

摘要： A method and apparatus for manufacturing an integrated circuit (IC), the method including, generating, by a graphical construction unit, a first graph corresponding to a first net of the IC, the first graph representing a pin of the first net as a vertex, and a connection between two pins of the first net as an edge, the first graph further corresponding to a first IC layout; identifying a first and a second pair of unconnected vertices in the first graph for inserting a first and a second redundant edge, respectively, the first redundant edge and the second redundant edge forming a first connected loop and a second connected loop, respectively, each loop further including at least two edges of the first graph; calculating a tolerance ratio for the first redundant edge and the second redundant edge; sorting the first and second redundant edge based on their tolerance ratio; calculating a yield rate change of the first IC layout associated with inserting one of the first or second redundant edge with a highest tolerance ratio, and updating the first IC layout to include the redundant edge with the highest tolerance ratio if the yield rate change is greater than zero; and calculating the yield rate change of the first IC layout associated with inserting the first or second redundant edge having a second highest tolerance ratio, and updating the first IC layout to include the redundant edge with the second highest tolerance ratio if the yield rate change is greater than zero.

摘要翻译： 一种用于制造集成电路（IC）的方法和装置，所述方法包括：通过图形构造单元生成与所述IC的第一网络对应的第一图形，所述第一图形表示所述第一网络的针脚作为顶点 以及第一网的两个引脚之间的连接作为边缘，第一图形还对应于第一IC布局; 识别第一图中的第一和第二对未连接顶点，分别插入第一和第二冗余边缘，第一冗余边缘和第二冗余边缘分别形成第一连接环路和第二连接环路，每个环路 还包括所述第一图形的至少两个边缘; 计算第一冗余边缘和第二冗余边缘的容差比; 根据其容差比对第一和第二冗余边进行排序; 计算与插入具有最高容差比的第一或第二冗余边缘之一相关联的第一IC布局的产出率变化，以及如果产出率变化较大，则更新第一IC布局以包括具有最高容差比的冗余边缘 比零; 以及计算与插入具有第二高容差比的第一或第二冗余边缘相关联的第一IC布局的产出率变化，并且如果产出率变化为更新，则将第一IC布局更新为包括具有第二高容差比的冗余边缘 大于零。