公开(公告)号：US08216904B2

公开(公告)日：2012-07-10

申请号：US12651217

申请日：2009-12-31

Applicant: Barry Dove

Inventor： Barry Dove

IPC: H01L21/762 ,  H01L27/088

CPC classification number: H01L29/7843 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/6659 ,  H01L29/7833

Abstract: According to one embodiment, a semiconductor substrate is provided having at least two transistor regions formed therein. Overlying the channel regions is a gate dielectric and transistor gate electrodes overly the gate dielectric and are positioned overlying the channel regions. Source and drain regions are formed on either side of the channel regions to create a transistor structure. In order to provide isolation between transistors in the semiconductor substrate, a trench is formed in the substrate. A strain-inducting layer is then deposited over the transistor structures and into the trench in the semiconductor substrate. A high-stress nitride layer is one type of material which is suitable for forming the strain-inducing layer.

Abstract translation: 根据一个实施例，提供了在其中形成有至少两个晶体管区域的半导体衬底。 覆盖沟道区域是栅极电介质和位于栅极电介质上方的晶体管栅电极，并且位于沟道区域上方。 源极和漏极区域形成在沟道区域的两侧以产生晶体管结构。 为了在半导体衬底中的晶体管之间提供隔离，在衬底中形成沟槽。 然后将应变诱导层沉积在晶体管结构上并进入半导体衬底中的沟槽中。 高应力氮化物层是适合于形成应变诱导层的一种材料。

公开(公告)号：US20060168433A1

公开(公告)日：2006-07-27

申请号：US11045822

申请日：2005-01-26

Applicant: Dillip Dash

Inventor： Dillip Dash

IPC: G06F9/44

CPC classification number: G06F9/325 ,  G06F9/30065 ,  G06F9/3853 ,  G06F9/3885

Abstract: A very long instruction word processor with sequence control. During each cycle the processor generates control signals to functional units based on the values in fields of an instruction. Each instruction may include an iteration count specifying the number of cycles for which the control signals should be generated based on that instruction. The instruction set further includes flow control instructions allowing for repetitive execution of a single instruction, repetitive execution of a block of instructions or branching within a program. Such a processor is illustrated in connection with a disk controller for a hard drive of a computer. The flexible sequencing allows a hard-drive controller to be readily reprogrammed for use in connection with different types of media or to be dynamically reprogrammed upon detection of a disk read error to increase the ability of the disk controller to recover data from a disk.

Abstract translation: 一个很长的指令字处理器，具有序列控制。 在每个周期期间，处理器基于指令的字段中的值来生成对功能单元的控制信号。 每个指令可以包括指定基于该指令来生成控制信号的周期数的迭代计数。 指令集还包括允许重复执行单个指令，重复执行指令块或在程序内分支的流控制指令。 这种处理器与用于计算机的硬盘驱动器的盘控制器相关联地示出。 灵活的排序允许硬盘驱动器控制器可以轻松地重新编程，以便与不同类型的介质连接使用，或者在检测到磁盘读取错误时进行动态重新编程，以增加磁盘控制器从磁盘中恢复数据的能力。

公开(公告)号：US20120042103A1

公开(公告)日：2012-02-16

申请号：US13279647

申请日：2011-10-24

Applicant: TAYLOR J. LEAMING

Inventor： TAYLOR J. LEAMING

IPC: G06F13/38

CPC classification number: G06K19/07

Abstract: An integrated circuit for a smart card in accordance with an exemplary embodiment includes at least one data terminal for providing communications with a host device over a system bus and a processor configured to provide an attachment signal on the at least one data terminal for recognition by the host device. Further, the processor also cooperates with the host device to perform an enumeration based upon at least one default descriptor, and receive information from the host device regarding a system event. In addition, the processor is configured to remove the attachment signal from the at least one data terminal and thereafter again provide the attachment signal on the at least one data terminal based upon the information regarding the system event, and cooperate with the host device to perform a new enumeration based upon at least one alternate descriptor.

Abstract translation: 根据示例性实施例的用于智能卡的集成电路包括至少一个数据终端，用于通过系统总线提供与主机设备的通信;以及处理器，被配置为在至少一个数据终端上提供附件信号以由 主机设备。 此外，处理器还与主机设备协作以基于至少一个默认描述符执行枚举，并且从主机设备接收关于系统事件的信息。 此外，处理器被配置为从至少一个数据终端移除附件信号，然后基于关于系统事件的信息再次在至少一个数据终端上提供附件信号，并与主机设备协作执行 基于至少一个替代描述符的新的枚举。

公开(公告)号：US20100241835A1

公开(公告)日：2010-09-23

申请号：US12748124

申请日：2010-03-26

Applicant: Stefano Cervini

Inventor： Stefano Cervini

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/383

Abstract: A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when an operand for an instruction is generated by another instruction. When operands for an instruction are available, that instruction is a “ready” instruction. A ready instruction is selected in each cycle and executed. To allow data to be transmitted between terminals, each terminal is provided with a receive station, such that data generated in one terminal may be transmitted to another terminal for use as an operand in that terminal. In one embodiment, one terminal is an arithmetic terminal, executing arithmetic operations such as addition, multiplication and division. The processor has a second terminal, which contains functional logic to execute all other instructions in the instruction set. The invention is useful for arithmetic intensive applications, such as graphic processors.

Abstract translation: 高速处理器 处理器包括各自执行指令集的子集的终端。 在至少一个终端中，以由数据流确定的顺序执行指令。 说明将以页面方式加载到终端中。 当指令的操作数由另一个指令生成时，进行符号化。 当指令的操作数可用时，该指令是“就绪”指令。 在每个周期中选择一个就绪指令并执行。 为了允许在终端之间传输数据，每个终端设置有接收站，使得在一个终端中生成的数据可以被发送到另一终端，以用作该终端中的操作数。 在一个实施例中，一个终端是算术终端，执行诸如加法，乘法和除法之类的算术运算。 处理器具有第二终端，其包含用于执行指令集中的所有其他指令的功能逻辑。 本发明对于诸如图形处理器的算术密集型应用是有用的。

公开(公告)号：US20130082257A1

公开(公告)日：2013-04-04

申请号：US13251352

申请日：2011-10-03

Applicant: Bahierathan Balasingham ,  Christopher B. D'Aleo ,  Gregory M. Johnson ,  Muthukumarasamy Karthikeyan ,  Shenzhi Yang

Inventor： Bahierathan Balasingham ,  Christopher B. D'Aleo ,  Gregory M. Johnson ,  Muthukumarasamy Karthikeyan ,  Shenzhi Yang

IPC: H01L23/48 ,  H01L21/66

CPC classification number: H01L22/30 ,  H01L22/14 ,  H01L22/20 ,  H01L22/34

Abstract: Method form via chain and serpentine/comb test structures in kerf areas of a wafer. The via chain test structures comprise a first via chain and a second via chain in a first kerf area. The via chain test structures are formed such that geometrically shaped portions of the first via chain and geometrically shaped portions of the second via chain alternate along the length of the first kerf area. The methods perform relatively low (first) magnification testing to identify a defective geometrically shaped portion that contains a defective via structure. The methods then perform relatively high (second) magnification testing only within the defective geometrically shaped portion. The first magnification testing is performed at a lower magnification relative to the second magnification testing.

Abstract translation: 通过链条和蛇纹石/梳状测试结构在晶片的切口区域中的方法形式。 通孔链测试结构包括在第一切口区域中的第一通孔链和第二通孔链。 通孔链测试结构被形成为使得第一通孔链的几何形状部分和第二通孔链的几何形状部分沿着第一切口区域的长度交替。 该方法执行相对较低（第一）倍率测试以识别包含有缺陷的通孔结构的有缺陷的几何形状的部分。 然后，该方法仅在缺陷几何形状部分内执行相对高（第二）放大率测试。 相对于第二倍率测试，以较低的放大倍数执行第一放大率测试。

公开(公告)号：US5920353A

公开(公告)日：1999-07-06

申请号：US758779

申请日：1996-12-03

Applicant: Raul Zegers Diaz ,  Jeyendran Balakrishnan ,  Jefferson Eugene Owen

Inventor： Raul Zegers Diaz ,  Jeyendran Balakrishnan ,  Jefferson Eugene Owen

IPC: H04N7/32 ,  H03M7/30 ,  H04N7/26 ,  H04N7/50

CPC classification number: H04N19/42 ,  H04N19/61

Abstract: Circuits and methods for subdividing a decoder into functional blocks that can be accessed separately. The decoder includes a decoder module having a parser, a block decoder and a motion compensation engine, which can all be further subdivided into functional blocks. The functional blocks can be bypassed in decompressing frames where the blocks are not necessary, or when the compression algorithm does not require the functional block, increasing the speed of the decoder. The functional blocks can also be reused for decompression or compression based on different standards, or for different operation in the decoder, such as decompression and compression. The decoder can be coupled to a processor and some of the functional block performed in the decoder's hardware and some are performed in the processor. In one embodiment of the invention and the processor determines which block are to be by-passed completely and which block are to be performed in software based on the decompression protocol to which the compressed frame is encoded to comply to, the capacity and speed of the processor, and the available memory. In another embodiment multiplexers can be added to the decoder to connect functional blocks so they can be by-passed or reused based on preprogramming of the multiplexers based on the decompression protocol to which the compressed frame is encoded to comply to, the capacity and speed of the processor, and the available memory.

Abstract translation: 将解码器细分为可单独访问的功能块的电路和方法。 解码器包括具有解析器，块解码器和运动补偿引擎的解码器模块，其可以进一步细分为功能块。 在不需要块的解压缩帧中，或者当压缩算法不需要功能块时，功能块可以被旁路，从而增加解码器的速度。 功能块也可以用于基于不同标准的解压缩或压缩，或用于解码器中的不同操作，例如解压缩和压缩。 解码器可以耦合到处理器，并且在解码器的硬件中执行的一些功能块和一些在处理器中执行。 在本发明的一个实施例中，处理器基于压缩帧被编码为符合的解压缩协议来确定哪个块将被完全地被旁路，以及哪个块将被软件执行，该容量和速度 处理器和可用内存。 在另一个实施例中，多路复用器可以被添加到解码器以连接功能块，使得它们可以基于基于压缩帧被编码的解压缩协议的多路复用器的预编程来被旁路或重新使用，以满足以下条件的容量和速度 处理器和可用内存。

公开(公告)号：US09230857B2

公开(公告)日：2016-01-05

申请号：US14522011

申请日：2014-10-23

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lindsey H. Hall ,  Michael Hatzistergos ,  Ahmet S. Ozcan ,  Filippos Papadatos ,  Yiyi Wang

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/321

CPC classification number: H01L21/76877 ,  H01L21/32115 ,  H01L21/32135 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76871 ,  H01L21/76892

Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.

公开(公告)号：US08222138B2

公开(公告)日：2012-07-17

申请号：US12698006

申请日：2010-02-01

Applicant: Ardeshir J. Sidhwa

Inventor： Ardeshir J. Sidhwa

IPC: H01L21/768

CPC classification number: C23C14/16 ,  C23C14/568 ,  C23C16/06 ,  C23C16/54 ,  H01L21/32051

Abstract: A thick metal layer is formed on a semiconductor integrated circuit in multiple different deposition chambers. A first portion of the metal layer is formed in a first deposition chamber, the first thickness being approximately half the target thickness. The substrate is then removed from the first chamber and transported to a second chamber. The deposition of the same metal layer continues in a second chamber, having the same grain structure and orientation. The second portion of the metal layer is grown to achieve the final thickness. By using two different deposition chambers to form the single metal layer, layers in excess of 25,000 angstroms in thickness can be obtained.

Abstract translation: 在多个不同的沉积室中的半导体集成电路上形成厚金属层。 金属层的第一部分形成在第一沉积室中，第一厚度大约是目标厚度的一半。 然后将基板从第一室移除并输送到第二室。 相同金属层的沉积在具有相同晶粒结构和取向的第二腔中继续。 生长金属层的第二部分以达到最终的厚度。 通过使用两个不同的沉积室来形成单个金属层，可以获得超过25,000埃厚度的层。

公开(公告)号：US20060149941A1

公开(公告)日：2006-07-06

申请号：US11013122

申请日：2004-12-15

Applicant: Osvaldo Colavin ,  Davide Rizzo ,  Vineet Soni

Inventor： Osvaldo Colavin ,  Davide Rizzo ,  Vineet Soni

IPC: G06F15/00

CPC classification number: G06F8/45 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30189 ,  G06F9/345 ,  G06F9/381 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3867

Abstract: A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times per fetch. In vector mode, the processor recognizes scalar variables and vector variables. Scalar variables may be assigned a fixed memory location. Vector variables use different physical locations at different iterations of the same instruction. The processor includes circuitry to automatically index addresses of vector variables for each iteration of the same instruction. This circuitry partitions a register into a vector region and a scalar region. Accesses to the vector region are automatically indexed based on the number of iterations of the instruction that have been performed.

公开(公告)号：US20060149929A1

公开(公告)日：2006-07-06

申请号：US11003248

申请日：2004-12-03

Applicant: Stefano Cervini

Inventor： Stefano Cervini

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/383

Abstract: A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when an operand for an instruction is generated by another instruction. When operands for an instruction are available, that instruction is a “ready” instruction. A ready instruction is selected in each cycle and executed. To allow data to be transmitted between terminals, each terminal is provided with a receive station, such that data generated in one terminal may be transmitted to another terminal for use as an operand in that terminal. In one embodiment, one terminal is an arithmetic terminal, executing arithmetic operations such as addition, multiplication and division. The processor has a second terminal, which contains functional logic to execute all other instructions in the instruction set. The invention is useful for arithmetic intensive applications, such as graphic processors.

Abstract translation: 高速处理器 处理器包括各自执行指令集的子集的终端。 在至少一个终端中，以由数据流确定的顺序执行指令。 说明将以页面方式加载到终端中。 当指令的操作数由另一个指令生成时，进行符号化。 当指令的操作数可用时，该指令是“就绪”指令。 在每个周期中选择一个就绪指令并执行。 为了允许在终端之间传输数据，每个终端设置有接收站，使得在一个终端中生成的数据可以被发送到另一终端，以用作该终端中的操作数。 在一个实施例中，一个终端是算术终端，执行诸如加法，乘法和除法之类的算术运算。 处理器具有第二终端，其包含用于执行指令集中的所有其他指令的功能逻辑。 本发明对于诸如图形处理器的算术密集型应用是有用的。