摘要:
Highly conducting polyaniline is produced in situ in a tantalum capacitor by subjecting an excess of monomeric aniline to a solution having a low concentration of ammonium persulfate reagent. The monomer is oxidized by the reagent in preference to the polymer, so that the presence of excess monomer protects the polymer as it is produced against further oxidation to a less conductive species.
摘要:
A solid electrolyte capacitor in a block of electrically insulative resin is provided with two electrodes connected by respective connecting tangs to output leads (+, -) and to a fuze test lead; one connecting tang (6) is formed by a first section (6B) fixed to one of the electrodes and projecting out of the resin block to form the fuze test lead, and a second section (6A) projecting out of the resin block to form a conventional terminal; an elongate strip (10) forms the fuze in one piece with the sections (6A,6B) so as to provide the only electrical connection between the sections; the fuze is coated with a supporting mass of thermally insulative resin extending between the two sections and embedded in the resin block.
摘要:
A standard tinned nickel-iron alloy lead frame has a plurality of pairs of extending tab portion positioned in a straight row. A long straight piece of an exothermically alloyable fuse wire, with a core of aluminum coaxially clad with palladium in approximately equal volumes, is held in contact with the plurality of pairs of lead frame tabs. Heat is applied to the fuse strand at two points; namely, on one and the other sides of each pair of tabs initiating progressive alloying in two directions from each heated point. When the progressive alloying and melting of the fuse strand reaches a tab, the tab is heated and heat sinks the fuse strand to stop the progressive alloying and melting. There is simultaneously formed a metallurgical bond between the ends of each remaining elemental fuse strand, respectively, and each of the pair of tabs that are bridged by that remaining elemental strand.
摘要:
The manufacture of an integrated circuit including an isolated vertical PNP, an isolated vertical NPN and isolated CMOS transistors is described. The PNP transistor has a shallow densely doped emitter made simultaneously with the source and drain of the PMOS transistor. The PNP base is made simultaneously with lightly doped portions of the LDD source and drain of the NMOS transistor. The PNP collector is made simultaneously with the P-well in which the NMOS transistor is formed. A P-buried layer in the isolated vertical PNP transistor provides a low collector resistance and is formed simultaneously with the P-buried layer of the NMOS transistor that extends the P-well there and better isolates the NMOS transistor from the substrate. And the N-buried layer providing superior isolation of the PNP with respect to the substrate is formed simultaneously with the N-buried layer of the vertical NPN transistor. All four of these transistors provide and are well suited for use in analog signal handling circuits. All are capable of operating at up to 15 volts. And both bipolar transistors have a high gain bandwidth.
摘要:
A solid electrolytic capacitor embedded in an electrically insulating resin block has a capacitor body fitted with two electrodes which are connected by two connecting lugs, those of the output terminals (+, -) and a fuze test. One of the connecting lugs is formed of a first section attached to one of electrodes of the capacitor body and leading outside the resin block to form the fuze test terminal, and of a second section electrically insulated with respect to first section and the capacitor body and leading outside the resin block to form a normal operating terminal. The fuze element alone establishes an electric link between the first and second sections while being surrounded by the supporting mass of thermally insulating resin reaching from one of the sections to the other, while itself being embedded in the resin.
摘要:
A Hall elements and magnet assembly for use as a proximity detector includes a magnet, a pole piece mounted to one pole end of the magnet and an integrated circuit having two side-by-side Hall elements, an amplifier, interconnecting wiring providing the difference voltage between the two Hall output voltages at the input of the amplifier, and a Schmitt trigger circuit. The integrated circuit is mounted to the pole piece at the pole end of the magnet. The pole piece is a ferromagnetic member which is thinner in the center than at the periphery for achieving a highly uniform field strength across the surface of the magnet pole end toward reducing the criticality of the position of mounting of the integrated circuit in manufacturing and for extending the range of gap dimensions between a passing ferromagnetic article and the assembly for which proper detection of the passing article can be made to occur. The term "ferromagnetic" as used herein means any material with a relative permeability greater than unity and preferably greater than 100.
摘要:
The method includes forming in one surface of an N+ silicon wafer a matrix of uniformly deep V-shaped grooves, growing one SiO.sub.2 over the one surface and the walls of the grooves, forming over the opposite wafer surface a thick self-supporting polycrystalline layer, progressively removing portions of the original silicon wafer until the bottoms of the grooves are detected to leave separate patches of the original N+ silicon wafer material and then growing a thin (e.g. 6 microns) P-doped layer of epitaxial silicon on the exposed N+ silicon layer patch portions now isolated and defined by the grooves. A figure-eight pattern of trenches is formed in each silicon island completely through the P epitaxial layer and each of the underlying N+ buried patches but stopped at the SiO.sub.2 layer. An N+ plug is formed through the epitaxial layer to each N+ patch. Metal conductors complete the formation of a JFET transistor in each island bounded and defined by one of the closed loops or annular portions of the figure-eight-patterned trenches. The wafer is then sawed apart along all the V-shaped grooves providing a plurality of IC die, each having two dielectrically isolated JFET transistors.
摘要:
A silicon integrated circuit includes a vertical power DMOS transistor and a vertical NPN transistor in separate epitaxial pockets by a method including simultaneously forming a plurality of D-well regions in the DMOS transistor and the base region in the NPN transistor, and including simultaneously forming the elemental source regions and the emitter region. N-type buried layers are provided simultaneously in the DMOS and the NPN transistors, respectively. Also formed simultaneously are two N+ plugs connecting the two buried layers, respectively, to the epitaxial surface of the integrated circuit die. None of these economically attractive simultaneous steps requires deviation in either device from optimum geometries. Also disclosed are compatible and integrated steps for forming small signal CMOS transistors. This method also includes a full self-alignment of gate, source and channel regions in the DMOS transistor as well as in the CMOS transistors.
摘要:
A solid electrolyte capacitor body is embedded in an electrically insulative block of resin. Output terminals each connected to a respective electrode of the capacitor body project from the block. One output terminal includes a first section fixed to one of the electrodes and a second section electrically insulated from the first section and the capacitor body. A fusible member alone establishes electrical connection between the first and second sections. The fusible member is embedded in a rigid thermally insulative resin which extends between the first and second sections to couple them together mechanically.
摘要:
A capacitor having a wound aluminum foil electrolytic capacitor section contains an electrolyte solution of 10 to 32 wt % diethylammonium fumarate, 10 to 30 wt % N-methylpyrrolidinone, 4 to 7 wt % water, 0.1 to 0.5 wt % ammonium dihydrogen phosphate, with the remainder ethylene glycol. The capacitor is capable of operation at temperatures up to 125.degree. C.