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    Method and apparatus for two-dimensional profiling of doping profiles of a material sample with scanning capacitance microscope
    2.
    发明申请
    Method and apparatus for two-dimensional profiling of doping profiles of a material sample with scanning capacitance microscope 有权
    用扫描电容显微镜对材料样品的掺杂分布进行二维分析的方法和装置

    公开(公告)号：US20070221841A1

    公开(公告)日：2007-09-27

    申请号：US11726590

    申请日：2007-03-22

    申请人： Guenther Benstetter ,  Peter Breitschopf ,  Bernhard Theo Knoll

    发明人： Guenther Benstetter ,  Peter Breitschopf ,  Bernhard Theo Knoll

    IPC分类号： G01N23/00

    CPC分类号： G01Q60/46

    摘要： A method and an apparatus is disclosed for two-dimensional profiling of doping profiles of a material sample with scanning capacitance microscope. A scanning of a two-dimensional structure of a dielectric or partially dielectric material sample with a tip of a probe of the scanning microscope is carried out. The change in capacitance during the scanning motion of the probe from one position on the material sample to the next is measured. Finally, an evaluation of the change in capacitance during the scanning motion of the probe from one position on the material sample to the next as a current is carried out.

    摘要翻译： 公开了一种利用扫描电容显微镜对材料样品的掺杂分布进行二维分析的方法和装置。 利用扫描显微镜的探针的尖端对电介质或部分电介质材料样品的二维结构进行扫描。 测量探针从材料样品上的一个位置到下一个位置的扫描运动期间电容的变化。 最后，对探针从材料样品上的一个位置到下一个位置的扫描运动中的电容变化进行评价。

    Method for measuring nm-scale tip-sample capacitance
    3.
    发明授权
    Method for measuring nm-scale tip-sample capacitance 失效
    测量nm尺度尖端样品电容的方法

    公开(公告)号：US07023220B2

    公开(公告)日：2006-04-04

    申请号：US10967930

    申请日：2004-10-19

    申请人： Jonathan P. Pelz ,  David T. Lee ,  Bharat Bhushan

    发明人： Jonathan P. Pelz ,  David T. Lee ,  Bharat Bhushan

    IPC分类号： G01R27/26

    CPC分类号： G01Q60/46 ,  G01R27/2605 ,  Y10S977/866

    摘要： A method for measuring nm-scale tip-sample capacitance including (a) measuring a cantilever deflection and a change in probe-sample capacitance relative to a reference level as a function of a probe assembly height; (b) fitting out-of-contact data to a function; (c) subtracting the function from capacitance data to get a residual capacitance as a function of the probe assembly height; and (d) determining the residual capacitance at a z-position where the cantilever deflection is zero.

    摘要翻译： 一种用于测量nm尺度尖端样本电容的方法，包括（a）测量悬臂偏转和相对于参考水平的探针样品电容的变化，作为探针组件高度的函数; （b）将不合格数据拟合到一个功能上; （c）从电容数据中减去该功能，以获得作为探头组件高度的函数的残余电容; 和（d）确定悬臂偏转为零的z位置处的残余电容。

    Semiconductor testing structures and fabrication method thereof
    5.
    发明授权
    Semiconductor testing structures and fabrication method thereof 有权
    半导体测试结构及其制造方法

    公开(公告)号：US09557348B2

    公开(公告)日：2017-01-31

    申请号：US14567362

    申请日：2014-12-11

    申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

    发明人： Nan Li ,  Lilung Lai ,  Ling Zhu

    IPC分类号： G01Q30/20 ,  G01Q60/46 ,  C23F1/00 ,  B32B37/18 ,  B32B38/10 ,  G01B21/20 ,  H01L21/66

    CPC分类号： G01Q60/46 ,  B32B37/18 ,  B32B38/10 ,  C23F1/00 ,  G01B21/20 ,  G01Q30/20 ,  H01L22/14

    摘要： A method is provided for fabricating a semiconductor testing structure. The method includes providing a substrate having a to-be-tested device structure formed on a surface of the substrate, a dielectric layer formed on the surface of the substrate and a surface of the to-be-tested structure, and conductive structures and an insulation layer electrically insulating the conductive structures formed on a first surface of the dielectric layer. The method also includes planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer until the first surface of the dielectric layer is exposed; and bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer. Further, the method includes removing the substrate to expose a second surface relative to the first surface of the dielectric layer of the dielectric layer and a surface of the to-be-tested device structure.

    摘要翻译： 提供了制造半导体测试结构的方法。 该方法包括提供具有形成在基板的表面上的被测试的器件结构的基板，形成在基板的表面上的电介质层和待测试结构的表面，以及导电结构和 绝缘层使形成在电介质层的第一表面上的导电结构电绝缘。 该方法还包括平坦化导电结构和绝缘层以去除导电结构和绝缘层，直到电介质层的第一表面露出为止; 以及通过粘合剂层将所述电介质层的第一表面与虚设晶片接合。 此外，该方法包括去除衬底以暴露相对于电介质层的电介质层的第一表面的第二表面和待测试器件结构的表面。

    SEMICONDUCTOR TESTING STRUCTURES AND FABRICATION METHOD THEREOF
    6.
    发明申请
    SEMICONDUCTOR TESTING STRUCTURES AND FABRICATION METHOD THEREOF 有权
    半导体测试结构及其制造方法

    公开(公告)号：US20150316583A1

    公开(公告)日：2015-11-05

    申请号：US14567362

    申请日：2014-12-11

    申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

    发明人： NAN LI ,  LILUNG LAI ,  LING ZHU

    IPC分类号： G01Q30/20 ,  G01B21/20 ,  B32B38/10 ,  C23F1/00 ,  B32B37/18

    CPC分类号： G01Q60/46 ,  B32B37/18 ,  B32B38/10 ,  C23F1/00 ,  G01B21/20 ,  G01Q30/20 ,  H01L22/14

    摘要： A method is provided for fabricating a semiconductor testing structure. The method includes providing a substrate having a to-be-tested device structure formed on a surface of the substrate, a dielectric layer formed on the surface of the substrate and a surface of the to-be-tested structure, and conductive structures and an insulation layer electrically insulating the conductive structures formed on a first surface of the dielectric layer. The method also includes planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer until the first surface of the dielectric layer is exposed; and bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer. Further, the method includes removing the substrate to expose a second surface relative to the first surface of the dielectric layer of the dielectric layer and a surface of the to-be-tested device structure.

    摘要翻译： 提供了制造半导体测试结构的方法。 该方法包括提供具有形成在基板的表面上的被测试的器件结构的基板，形成在基板的表面上的电介质层和待测试结构的表面，以及导电结构和 绝缘层使形成在电介质层的第一表面上的导电结构电绝缘。 该方法还包括平坦化导电结构和绝缘层以去除导电结构和绝缘层，直到电介质层的第一表面露出为止; 以及通过粘合剂层将所述电介质层的第一表面与虚设晶片接合。 此外，该方法包括去除衬底以暴露相对于电介质层的电介质层的第一表面的第二表面和待测试器件结构的表面。

    PROBE-BASED DATA COLLECTION SYSTEM WITH ADAPTIVE MODE OF PROBING CONTROLLED BY LOCAL SAMPLE PROPERTIES
    7.
    发明申请
    PROBE-BASED DATA COLLECTION SYSTEM WITH ADAPTIVE MODE OF PROBING CONTROLLED BY LOCAL SAMPLE PROPERTIES 审中-公开
    基于探针的数据采集系统，具有由本地样品特性控制的自适应探测模式

    公开(公告)号：US20140380531A1

    公开(公告)日：2014-12-25

    申请号：US14314013

    申请日：2014-06-24

    申请人： DCG Systems, Inc.

    发明人： Vladimir A. Ukraintsev ,  Richard Stallcup ,  Sergiy Pryadkin ,  Mike Berkmyre ,  John Sanders

    IPC分类号： G01Q10/04

    CPC分类号： G01R31/31728 ,  G01Q10/065 ,  G01Q30/04 ,  G01Q60/10 ,  G01Q60/18 ,  G01Q60/30 ,  G01Q60/46 ,  G01R31/311

    摘要： A method for testing an integrated circuit (IC) using a nanoprobe, by using a scanning electron microscope (SEM) to register the nanoprobe to an identified feature on the IC; navigating the nanoprobe to a region of interest; scanning the nanoprobe over the surface of the IC while reading data from the nanoprobe; when the data from the nanoprobe indicates that the nanoprobe traverse a feature of interest, decelerating the scanning speed of the nanoprobe and performing testing of the IC. The scanning can be done at a prescribed nanoprobe tip force, and during the step of decelerating the scanning speed, the method further includes increasing the nanoprobe tip force.

    摘要翻译： 一种使用纳米探针测试集成电路（IC）的方法，通过使用扫描电子显微镜（SEM）将纳米探针登记到IC上的识别特征; 将纳米探针导航到感兴趣的区域; 在从纳米探针读取数据的同时，在IC表面上扫描纳米探针; 当来自纳米探针的数据指示纳米探针穿过感兴趣的特征时，减小纳米探针的扫描速度并执行IC的测试。 可以以规定的纳米探针前端力进行扫描，并且在扫描速度减速的步骤中，该方法还包括增加纳米探针末端力。

    SEMICONDUCTOR TESTING STRUCTURES AND SEMICONDUCTOR TESTING APPARATUS
    10.
    发明申请
    SEMICONDUCTOR TESTING STRUCTURES AND SEMICONDUCTOR TESTING APPARATUS 审中-公开
    半导体测试结构和半导体测试设备

    公开(公告)号：US20170016934A1

    公开(公告)日：2017-01-19

    申请号：US15280777

    申请日：2016-09-29

    申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

    发明人： Nan LI ,  Lilung LAI ,  Ling ZHU

    IPC分类号： G01Q60/46

    CPC分类号： G01Q60/46 ,  B32B37/18 ,  B32B38/10 ,  C23F1/00 ,  G01B21/20 ,  G01Q30/20 ,  H01L22/14

    摘要： A method is provided for fabricating a semiconductor testing structure. The method includes providing a substrate having a to-be-tested device structure formed on a surface of the substrate, a dielectric layer formed on the surface of the substrate and a surface of the to-be-tested structure, and conductive structures and an insulation layer electrically insulating the conductive structures formed on a first surface of the dielectric layer. The method also includes planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer until the first surface of the dielectric layer is exposed; and bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer. Further, the method includes removing the substrate to expose a second surface relative to the first surface of the dielectric layer of the dielectric layer and a surface of the to-be-tested device structure.

    摘要翻译： 提供了制造半导体测试结构的方法。 该方法包括提供具有形成在基板的表面上的被测试的器件结构的基板，形成在基板的表面上的电介质层和待测试结构的表面，以及导电结构和 绝缘层使形成在电介质层的第一表面上的导电结构电绝缘。 该方法还包括平坦化导电结构和绝缘层以去除导电结构和绝缘层，直到电介质层的第一表面露出为止; 以及通过粘合剂层将所述电介质层的第一表面与虚设晶片接合。 此外，该方法包括去除衬底以暴露相对于电介质层的电介质层的第一表面的第二表面和待测试器件结构的表面。