公开(公告)号：US4885538A

公开(公告)日：1989-12-05

申请号：US291956

申请日：1988-12-29

申请人： John C. Hoenniger, III ,  Kenneth E. Hosier, Jr.

发明人： John C. Hoenniger, III ,  Kenneth E. Hosier, Jr.

IPC分类号： G01N24/00 ,  A61B5/055 ,  G01R33/48 ,  G01R33/54 ,  G05B19/042

CPC分类号： G01R33/54 ,  G05B19/0423 ,  G05B2219/21097 ,  G05B2219/25037 ,  G05B2219/25051 ,  G05B2219/25197 ,  G05B2219/25241 ,  G05B2219/25267

摘要： A data communications network for magnetic resonance imaging (MRI) systems provides characteristics ideal for low noise operation and low cost at speeds as high as 1 Mbytes/sec and provides a serial data bus for performing medium speed control and data acquisition functions. System architecture is extremely versatile and also low in cost. Each node of the communications system may be provided with an interface implemented with electronically programmable array logic (EPLD) applications specific integrated circuits (ASIC) with 1800 equivalent gates per CMOS integrated circuit. The resulting chip set is self clocking (no local oscillator is required) and nominally provides 20 bits of latched output and input with parity checking in a four-chip set configuration. A minimal two-chip set configuration can be used for nodes that need only 4 bits of latched input and output data (while still supporting parity checking). Different types of peripherals can easily be accommodated, and the bus is self configuring.

公开(公告)号：US4682168A

公开(公告)日：1987-07-21

申请号：US898854

申请日：1986-08-20

申请人： Paul S. Chang ,  Edward C. Dowling

发明人： Paul S. Chang ,  Edward C. Dowling

IPC分类号： G08C15/12 ,  G08C19/00 ,  G05B23/02 ,  H04Q11/00

CPC分类号： G08C15/12 ,  G05B2219/21037 ,  G05B2219/25051 ,  G05B2219/25315 ,  G05B2219/25321 ,  G05B2219/25324

摘要： A time-slot addressed, system keyed multiplex device is taught. Briefly stated, a ribbon cable provides a power and ground lead and a clock and data signal lead. A microcomputer or master controller then communicates over the ribbon cable with a plurality of intelligent connectors. Each connector is provided with a unique address such that by counting the number of clock pulses provided by the master controller the logic packages in the intelligent connector recognizes the appropriate time-slot for a response or command signal. A single one-pulse command is then presented by the master controller on the data bus which is then received by the logic circuitry followed by a time period on the data bus when the logic package may send to the master controller a single bit of data. In this manner of command and response, various devices such as relays may be turned on or off with their conditions presented to the master controller.

摘要翻译： 教授了一个时隙寻址系统密钥多路复用器件。 简要说明，带状电缆提供电源和接地引线以及时钟和数据信号引线。 微型计算机或主控制器然后通过带状电缆与多个智能连接器进行通信。 每个连接器具有唯一的地址，使得通过对由主控制器提供的时钟脉冲的数量进行计数，智能连接器中的逻辑包识别用于响应或命令信号的适当的时隙。 然后，主控制器在数据总线上呈现单个单脉冲命令，然后在逻辑包可以向主控制器发送单位数据时，逻辑电路接收数据总线上的时间段。 以这种命令和响应的方式，可以将各种设备（例如继电器）以其呈现给主控制器的条件打开或关闭。

公开(公告)号：US4808994A

公开(公告)日：1989-02-28

申请号：US89838

申请日：1987-08-27

申请人： Robert E. Riley

发明人： Robert E. Riley

IPC分类号： G05B15/02 ,  G05B19/042 ,  G05B19/07 ,  G08C15/12 ,  H04L7/00 ,  H04Q1/00

CPC分类号： G05B19/07 ,  G05B19/042 ,  G08C15/12 ,  G05B2219/21037 ,  G05B2219/21038 ,  G05B2219/24061 ,  G05B2219/25051 ,  G05B2219/25314 ,  G05B2219/25315 ,  G05B2219/25324 ,  G05B2219/25333 ,  H04L7/0008

摘要： A system for remotely controlling electrical devices includes a plurality of identical modules which can be made as multiple copies of an integrated circuit chip. Each chip includes logic for recognizing a code, the logic being programmable by EEPROMs so that each chip can be set to recognize a unique address code. The modules can be connected to input or output devices, or both. All modules are interconnected by no more than four wires. A clock pulse source is connected to the system, the source being periodically interrupted to synchronize the system when the clock pulses restart.

公开(公告)号：US5555267A

公开(公告)日：1996-09-10

申请号：US99788

申请日：1993-07-30

申请人： George E. Burke, Jr. ,  George M. Horne ,  Michael B. Carter

发明人： George E. Burke, Jr. ,  George M. Horne ,  Michael B. Carter

IPC分类号： H04L5/22 ,  G05B19/042 ,  G05B19/07 ,  G08C15/06 ,  H04J3/02 ,  H04Q9/00 ,  H04J3/00

CPC分类号： G08C15/06 ,  G05B19/0423 ,  G05B19/07 ,  H04J3/02 ,  G05B2219/21037 ,  G05B2219/25051 ,  G05B2219/25315 ,  G05B2219/25321 ,  G05B2219/25324 ,  G05B2219/25333 ,  G05B2219/25334

摘要： A control system (FIGS. 2, 3, 5, 6) and method in which multiple levels, or stages (128, 130, 132), of logical decisions are made by selectively feedforwarding output signals (356) from control modules (72) to the inputs of other modules (80), preferably through use of control modules (233) with selective feedforwarding circuits (239, 240) to logically combine during selected synchronous time slots (351) of a synchronous clock signal (FIG. 11) the result of a plurality of nonconcurrent input signals from a plurality of input devices (28, 30, 32, 34) to control an output device (26).

摘要翻译： 通过从控制模块（72）选择性地前馈输出信号（356）来进行逻辑决策的多个级别（128,130,132）的控制系统（图2，3，5，6）和方法， 优选地通过使用具有选择性前馈电路（239,240）的控制模块（233）来在其他模块（80）的输入端，以在同步时钟信号（图11）的选定的同步时隙（351）期间进行逻辑组合 来自多个输入设备（28,30,32,34）的多个非并发输入信号的结果来控制输出设备（26）。