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    DEEP LEARNING ARCHITECTURE FOR ADVERSE MEDIA SCREENING
    3.
    发明公开
    DEEP LEARNING ARCHITECTURE FOR ADVERSE MEDIA SCREENING 审中-公开

    公开(公告)号：US20240104347A1

    公开(公告)日：2024-03-28

    申请号：US17950153

    申请日：2022-09-22

    Applicant: Bank of America Corporation

    Inventor： Prashant Anna Bidkar ,  Ranjan Verma ,  T R Krishnan ,  Prashant Khare ,  Pradeep Gahtori ,  Vihar Sharoff

    IPC: G06N3/04 ,  G06N3/067

    CPC classification number: G06N3/0454 ,  G06N3/0675

    Abstract: Systems, methods, and apparatus are provided for deep learning architecture for adverse media screening. A dynamic data stream may be generated from news reports acquired from a variety of media channels in a variety of formats. Reports may be separated by format. A graphing module for each type of media may use geometric clustering algorithms to group reports into a coherence graph. Fact-checking sources may be incorporated into the graph. A graph neural network may determine coherence between news claims and fact-checking sources, between news claims and supporting report details, between similar reports, and/or between video and audio within the report itself. The network may output a legitimacy score for a report. A credible report may be flagged and retrieved in the course of a customer screening. Materiality may be determined for a credible report and may trigger a customer account closure protocol.

    Two-dimensional photonic neural network convolutional acceleration chip based on series connection structure
    4.
    发明授权
    Two-dimensional photonic neural network convolutional acceleration chip based on series connection structure 有权

    公开(公告)号：US11934943B1

    公开(公告)日：2024-03-19

    申请号：US18237839

    申请日：2023-08-24

    Applicant: ZHEJIANG LAB

    Inventor： Qingshui Guo ,  Kun Yin

    IPC: G06N3/067 ,  G06N3/049

    CPC classification number: G06N3/0675 ,  G06N3/049

    Abstract: The present invention discloses a two-dimensional photonic neural network convolutional acceleration chip based on series connection structure, which is integrated with a modulator, M microring delay weighting units, M−1 secondary delay waveguide, a wavelength-division multiplexer and a photodetector. Based on microring resonator arrays in M microring delay weighting units, the weighting of any convolution kernel matrix coefficient of the signal to be convolved is realized by the present invention, the refresh speed is fast, and real-time feedback training can be realized to extract the optimal convolution kernel matrix; in the present invention, realizing the primary wavelength-time interleaving of the sub weighted modulated signals with different wavelengths through the cascaded integrated waveguide between the microring resonators, realizing the secondary wavelength-time interleaving of sub-weighted modulated signals of different wavelengths by connecting the microring delay weighting units in series through the secondary delay waveguide, which can realize the delay multiplexing of the delay waveguide, comparing to parallel connection structure, it reduces the signal transmission loss caused by the delay waveguide while reducing the chip size, thereby improving the energy utilization efficiency of the chip.

    OPTOELECTRONIC COMPUTING SYSTEMS
    5.
    发明公开
    OPTOELECTRONIC COMPUTING SYSTEMS 审中-公开

    公开(公告)号：US20240078422A1

    公开(公告)日：2024-03-07

    申请号：US18216134

    申请日：2023-06-29

    Applicant: Lightelligence PTE. Ltd.

    Inventor： Huaiyu Meng ,  Yichen Shen ,  Yelong Xu ,  Gilbert Hendry ,  Longwu Ou ,  Jingdong Deng ,  Ronald Gagnon ,  Cheng-Kuan Lu ,  Maurice Steinman ,  Mike Evans ,  Jianhua Wu

    IPC: G06N3/067 ,  G06E1/04

    CPC classification number: G06N3/0675 ,  G06E1/045

    Abstract: An optoelectronic computing system includes a first semiconductor die having a photonic integrated circuit (PIC) and a second semiconductor die having an electronic integrated circuit (EIC). The PIC includes optical waveguides, in which input values are encoded on respective optical signals carried by the optical waveguides. The PIC includes an optical copying distribution network having optical splitters. The PIC includes an array of optoelectronic circuitry sections, each receiving an optical wave from one of the output ports of the optical copying distribution network, and each optoelectronic circuitry section includes: at least one photodetector detecting at least one optical wave from the optoelectronic operation. The EIC includes electrical input ports receiving respective electrical values. The first semiconductor die and the second semiconductor die are electrically coupled in a controlled collapse chip connection, with the electrical output port of the PIC connected to one of the electrical input ports of the EIC.

    Optoelectronic computing systems
    7.
    发明授权
    Optoelectronic computing systems 有权

    公开(公告)号：US11853871B2

    公开(公告)日：2023-12-26

    申请号：US17980079

    申请日：2022-11-03

    Applicant: Lightelligence PTE. Ltd.

    Inventor： Huaiyu Meng ,  Yichen Shen ,  Arash Hosseinzadeh ,  Yelong Xu ,  Yanfei Bai ,  Ronald Gagnon ,  Cheng-Kuan Lu ,  Jonathan Terry ,  Jingdong Deng ,  Maurice Steinman

    IPC: H04B10/54 ,  G02F1/21 ,  G06N3/067 ,  G06N3/04 ,  G06F17/16 ,  G02F1/225

    CPC classification number: G06N3/0675 ,  G02F1/225 ,  G06F17/16 ,  G06N3/04 ,  H04B10/541 ,  G02F1/212 ,  G02F2203/05

    Abstract: A system includes a first unit configured to generate a plurality of modulator control signals, and a processor unit. The processor unit includes: a light source or port configured to provide a plurality of light outputs, and a first set of optical modulators coupled to the light source or port and the first unit. The optical modulators in the first set are configured to generate an optical input vector by modulating the plurality of light outputs provided by the light source or port based on digital input values corresponding to a first set of modulator control signals in the plurality of modulator control signals, the optical input vector comprising a plurality of optical signals. The processor unit also includes a matrix multiplication unit that includes a second set of optical modulators. The matrix multiplication unit is coupled to the first unit, and is configured to transform the optical input vector into an analog output vector based on a plurality of digital weight values corresponding to a second set of modulator control signals in the plurality of modulator control signals applied to the second set of optical modulators. At least one optical modulator of at least one of the first set of optical modulators or the second set of optical modulators is configured to modulate an optical signal based on a first modulator control signal among the plurality of modulator control signals, and the first unit is configured to shape the first modulator control signal to include bandwidth-enhancement associated with a change in amplitude associated with a corresponding change in successive digital values corresponding to the first modulator control signal.

    SERIALIZED ELECTRO-OPTIC NEURAL NETWORK USING OPTICAL WEIGHTS ENCODING
    10.
    发明申请
    SERIALIZED ELECTRO-OPTIC NEURAL NETWORK USING OPTICAL WEIGHTS ENCODING 审中-公开

    公开(公告)号：US20190244090A1

    公开(公告)日：2019-08-08

    申请号：US16268578

    申请日：2019-02-06

    Applicant: Dirk Robert Englund

    Inventor： Dirk Robert Englund

    IPC: G06N3/067 ,  G06N3/08 ,  G06N3/04

    CPC classification number: G06N3/0675 ,  G06N3/04 ,  G06N3/08

    Abstract: Most artificial neural networks are implemented electronically using graphical processing units to compute products of input signals and predetermined weights. The number of weights scales as the square of the number of neurons in the neural network, causing the power and bandwidth associated with retrieving and distributing the weights in an electronic architecture to scale poorly. Switching from an electronic architecture to an optical architecture for storing and distributing weights alleviates the communications bottleneck and reduces the power per transaction for much better scaling. The weights can be distributed at terabits per second at a power cost of picojoules per bit (versus gigabits per second and femtojoules per bit for electronic architectures). The bandwidth and power advantages are even better when distributing the same weights to many optical neural networks running simultaneously.

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