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    Common mode signal detector
    2.
    发明授权
    Common mode signal detector 失效
    共模信号检测器

    公开(公告)号：US4518870A

    公开(公告)日：1985-05-21

    申请号：US539619

    申请日：1983-10-06

    申请人： Mihai Banu

    发明人： Mihai Banu

    IPC分类号： G01R19/10 ,  G06G7/14 ,  H03F3/45

    CPC分类号： H03F3/45183 ,  G06G7/14 ,  H03F3/45659 ,  H03F2203/45214 ,  H03F2203/45401 ,  H03F2203/45648 ,  H03F2203/45711

    摘要： A common mode detector (10) for producing an output voltage (VA+VB)/2 in response to input voltages VA and VB contains a pair of MOS transistors (MA and MB) connected in series between a pair of input terminals A and B to which the input voltages (VA and VB) are to be applied. A separate feedback path runs from each input terminal (A, B) through a separate load device (LA2, LB2) to a gate control terminal of the respective MOS transistor (MA, MB), and a separate other feedback path runs from each input terminal (A, B) through a separate other load device (LA3, LB3) to a substrate terminal (SA, SB) of the respective MOS transistors. In this way, the respective feedback paths deliver to the respective gate terminals respective voltages equal to (VDD+VA)/2 and (VDD+VB)/2, respectively, while the other feedback paths deliver to the substrates of the respective MOS transistors (MA, MB) respective substrate bias voltages equal to (VSS+VA)/2 and (VSS+VB)/2, whereby the common mode voltage (VA+VB)/2 is developed at a node (AB) between the pair of MOS transistors (MA, MB).

    摘要翻译： 用于响应于输入电压VA和VB产生输出电压（VA + VB）/ 2的共模检测器（10）包含串联连接在一对输入端子A和B之间的一对MOS晶体管（MA和MB） 要施加输入电压（VA和VB）。 单独的反馈路径从每个输入端子（A，B）通过单独的负载装置（LA2，LB2）运行到相应MOS晶体管（MA，MB）的栅极控制端子，并且另外的另一个反馈路径从每个输入端 端子（A，B）通过单独的另一个负载装置（LA3，LB3）连接到各个MOS晶体管的衬底端子（SA，SB）。 以这种方式，各个反馈通路分别传送到相应的栅极端子各自的等于（VDD + VA）/ 2和（VDD + VB）/ 2的电压，而其它反馈路径传送到各个MOS晶体管的基板 （MA，MB）各自的衬底偏置电压等于（VSS + VA）/ 2和（VSS + VB）/ 2，由此在该对之间的节点（AB）处形成共模电压（VA + VB）/ 2 的MOS晶体管（MA，MB）。

    OPERATIONAL AMPLIFIER INPUT OFFSET CORRECTION WITH TRANSISTOR THRESHOLD VOLTAGE ADJUSTMENT
    4.
    发明申请
    OPERATIONAL AMPLIFIER INPUT OFFSET CORRECTION WITH TRANSISTOR THRESHOLD VOLTAGE ADJUSTMENT 有权
    运算放大器输入偏移校正与晶体管阈值电压调整

    公开(公告)号：US20160056780A1

    公开(公告)日：2016-02-25

    申请号：US14463568

    申请日：2014-08-19

    申请人： MIE Fujitsu Semiconductor Limited

    发明人： Augustine Kuo

    IPC分类号： H03F3/45

    CPC分类号： H03F1/0272 ,  H01L29/7851 ,  H03F3/45183 ,  H03F3/45901 ,  H03F2203/45112 ,  H03F2203/45214 ,  H03F2203/45342 ,  H03F2203/45674

    摘要： A device can include an operational amplifier (op amp) circuit having a differential transistor pair, a first transistor of the differential transistor pair being formed in a first well of a substrate and a second transistor of the differential transistor pair being formed in a second well of the substrate; a body bias generator configured to generate at least a first body bias voltage for the first well, and not the second well, that varies in response to a first body bias control value; and a control circuit configured to selectively generate the first body bias control value in response to an input offset voltage of the op amp.

    摘要翻译： 器件可以包括具有差分晶体管对的运算放大器（运算放大器）电路，差分晶体管对的第一晶体管形成在衬底的第一阱中，差分晶体管对的第二晶体管形成在第二阱中 的基底; 身体偏置发生器，被配置为产生响应于第一身体偏置控制值变化的第一井而不是第二井的至少第一体偏置电压; 以及控制电路，被配置为响应于所述运算放大器的输入偏移电压选择性地产生所述第一体偏置控制值。

    High voltage, low-offset operational amplifier with rail-to-rail common mode input range in a digital CMOS process
    5.
    发明授权
    High voltage, low-offset operational amplifier with rail-to-rail common mode input range in a digital CMOS process 有权
    高电压，低失调运算放大器，在数字CMOS工艺中具有轨到轨共模输入范围

    公开(公告)号：US07064609B1

    公开(公告)日：2006-06-20

    申请号：US10919757

    申请日：2004-08-17

    申请人： Riley D. Beck ,  Aaron M. Shreeve

    发明人： Riley D. Beck ,  Aaron M. Shreeve

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45188 ,  H03F3/3022 ,  H03F3/45744 ,  H03F2203/45212 ,  H03F2203/45214 ,  H03F2203/45342 ,  H03F2203/45366 ,  H03F2203/45681

    摘要： An operational amplifier with two differential pairs coupled to different current sources. The gate terminals of the transistors in the first differential pair are used as input terminals providing common mode input for most of the rail-to-rail voltage. The bulk terminals of the transistors in the second differential pair are used as input terminals providing common mode input for the remainder of the rail-to-rail voltage to thereby accomplish full rail-to-rail common mode. By using the bulk terminals of the field effect transistors in the second differential pair, rather than the gate terminals, as the input terminal, the operational amplifier may be constructing in a single well, thereby being compatible with standard digital CMOS processes. Alternatively, the bulk-driven transistors may be replaced with gate-driven depletion type transistors. The high voltage transistors in the output stage further reduce the offset voltage of the operational amplifier.

    摘要翻译： 具有耦合到不同电流源的两个差分对的运算放大器。 第一差分对中的晶体管的栅极端子用作为大多数轨至轨电压提供共模输入的输入端。 第二差分对中的晶体管的体积端子用作为轨至轨电压的其余部分提供共模输入的输入端子，从而实现完整的轨到轨共模。 通过使用第二差分对中的场效应晶体管的体积端子而不是栅极端子作为输入端子，可以在单个阱中构建运算放大器，从而与标准数字CMOS工艺兼容。 或者，体驱动晶体管可以被栅极驱动的耗尽型晶体管代替。 输出级中的高电压晶体管进一步降低了运算放大器的失调电压。

    Operational amplifier input offset correction with transistor threshold voltage adjustment
    8.
    发明授权
    Operational amplifier input offset correction with transistor threshold voltage adjustment 有权
    晶体管阈值电压调节的运算放大器输入偏移校正

    公开(公告)号：US09319013B2

    公开(公告)日：2016-04-19

    申请号：US14463568

    申请日：2014-08-19

    申请人： MIE Fujitsu Semiconductor Limited

    发明人： Augustine Kuo

    IPC分类号： H03F3/45

    CPC分类号： H03F1/0272 ,  H01L29/7851 ,  H03F3/45183 ,  H03F3/45901 ,  H03F2203/45112 ,  H03F2203/45214 ,  H03F2203/45342 ,  H03F2203/45674

    摘要： A device can include an operational amplifier (op amp) circuit having a differential transistor pair, a first transistor of the differential transistor pair being formed in a first well of a substrate and a second transistor of the differential transistor pair being formed in a second well of the substrate; a body bias generator configured to generate at least a first body bias voltage for the first well, and not the second well, that varies in response to a first body bias control value; and a control circuit configured to selectively generate the first body bias control value in response to an input offset voltage of the op amp.

    摘要翻译： 器件可以包括具有差分晶体管对的运算放大器（运算放大器）电路，差分晶体管对的第一晶体管形成在衬底的第一阱中，差分晶体管对的第二晶体管形成在第二阱中 的基底; 身体偏置发生器，被配置为产生响应于第一身体偏置控制值变化的第一井而不是第二井的至少第一体偏置电压; 以及控制电路，被配置为响应于所述运算放大器的输入偏移电压选择性地产生所述第一体偏置控制值。

    Static method to negate offset voltages in CMOS operational amplifiers
    9.
    发明授权
    Static method to negate offset voltages in CMOS operational amplifiers 失效
    静态方法来否定CMOS运算放大器中的失调电压

    公开(公告)号：US4948992A

    公开(公告)日：1990-08-14

    申请号：US265113

    申请日：1988-10-31

    申请人： Eugene R. Bukowski, Jr.

    发明人： Eugene R. Bukowski, Jr.

    IPC分类号： H03F3/34 ,  H03F3/45

    CPC分类号： H03F3/45968 ,  H03F2203/45214 ,  H03F2203/45342

    摘要： Disclosed is a generator and method for using the generator to negate offset voltages in operational amplifiers. The generator includes an operational amplifier (op amp) whose input stage includes a current source coupled to a differential pair of input devices. The physical characteristics of the devices are such that an intentional offset voltage greater than the normal op amp offset voltage is provided in the input stage. The output terminal of the generator op amp is connected to the substrate terminal of one of the input devices. The offset voltages of other op amps can be negated by interconnecting the substrate terminal of one device in each input differential pair to the output terminal of the generator op amp and creating an intentional offset voltage in the input differential pair of each op amp.

    Circuit for limiting voltage differential in differential amplifiers
    10.
    发明授权
    Circuit for limiting voltage differential in differential amplifiers 失效
    用于限制差分放大器电压差的电路

    公开(公告)号：US4206418A

    公开(公告)日：1980-06-03

    申请号：US921207

    申请日：1978-07-03

    申请人： Andrew G. F. Dingwall

    发明人： Andrew G. F. Dingwall

    IPC分类号： H03F3/45 ,  H03K17/0812

    CPC分类号： H03F3/45183 ,  H03K17/08122 ,  H03F2203/45214 ,  H03F2203/45552

    摘要： The circuit includes means for limiting the potential difference that can exist between corresponding electrodes of two input transistors interconnected to form a differential amplifier stage. The control electrode of each input transistor is coupled via a normally conducting gating transistor to its respective input terminal and via a normally non-conducting clamping transistor to a common point to which is connected one end (source or emitter) of the main conduction paths of the two input transistors. In response to an input signal at an input terminal having a polarity and a first value to turn off an input transistor, the gating transistor is turned off and decouples the control electrode of the input transistor from its corresponding input terminal. Then, as the input signal increases beyond the first value in a direction to further reverse bias the input transistor, the clamping transistor is turned on and clamps the control electrode of the input transistor to the common point. The circuit may also include means connected to the output (drain or collector) electrodes of the two input transistor to prevent excessive voltage differentials between their output electrodes.

    摘要翻译： 电路包括用于限制互连以形成差分放大器级的两个输入晶体管的相应电极之间可能存在的电位差的装置。 每个输入晶体管的控制电极通过正常导通的选通晶体管耦合到其相应的输入端，并且经由正常非导通的钳位晶体管耦合到公共点，该公共点连接到主导通路径的一端（源极或发射极） 两个输入晶体管。 响应于具有极性和第一值的输入端的输入信号以截止输入晶体管，门控晶体管截止并将输入晶体管的控制电极与其相应的输入端分离。 然后，随着输入信号在输入晶体管的进一步反向偏置的方向上增加超过第一值，钳位晶体管导通并将输入晶体管的控制电极钳位到公共点。 电路还可以包括连接到两个输入晶体管的输出（漏极或集电极）电极的装置，以防止它们的输出电极之间的过大的电压差。