Driver circuit with pull down npn transistor and gain reduction
    1.
    发明授权
    Driver circuit with pull down npn transistor and gain reduction 失效
    驱动电路采用下拉式npn晶体管和增益减小

    公开(公告)号:US6072341A

    公开(公告)日:2000-06-06

    申请号:US853497

    申请日:1997-05-08

    CPC classification number: H03F1/32 H03F3/3088

    Abstract: A driver circuit with pull down npn transistor drives an output voltage signal in response to an input voltage signal, without high-speed pnp transistors. A first npn transistor provides current to the output node when the output node is at a level equal to and less than the level of the input voltage signal less a base-to-emitter junction drop across the first npn transistor. A second npn transistor sinks current from the output node when the output node is at a level greater than the level of the input voltage signal less the base-to-emitter junction drop across the first npn transistor. The second npn transistor is controlled by a level of a control node. When the level of the output node is greater than the level of the input voltage signal less the base-to-emitter junction drop, the first npn transistor is turned off and the level of the control node is charged up by a current source. When the level of the control node reaches a sufficient level, the second npn transistor is turned on and the level of the output voltage signal is decreased.

    Abstract translation: 具有下拉npn晶体管的驱动器电路响应于输入电压信号而驱动输出电压信号,而没有高速pnp晶体管。 当输出节点处于等于并且小于输入电压信号的电平的电平时,第一npn晶体管向输出节点提供电流,减去跨越第一npn晶体管的基极 - 发射极结降。 当输出节点处于大于输入电压信号的电平的电平时,第二个npn晶体管从输出节点吸收电流,减少了跨越第一npn晶体管的基极 - 发射极结降。 第二npn晶体管由控制节点的电平控制。 当输出节点的电平大于输入电压信号的电平时,基极 - 发射极结降低,第一个npn晶体管关闭,并且控制节点的电平由电流源充电。 当控制节点的电平达到足够的电平时,第二个npn晶体管导通,输出电压信号的电平降低。

    Power amplifier for rectangular input signals
    2.
    发明授权
    Power amplifier for rectangular input signals 失效
    功率放大器用于矩形输入信号

    公开(公告)号:US5142245A

    公开(公告)日:1992-08-25

    申请号:US685267

    申请日:1991-04-12

    Applicant: Stephane Barbu

    Inventor: Stephane Barbu

    CPC classification number: H03K19/001 H03F3/3088 H03K17/666

    Abstract: A power-amplifier cell which comprises an inverting input amplifier made up of a first transistor (T.sub.1) having a collector connected to a first supply-voltage terminal via a first resistor (R.sub.11), and an output stage comprising a second (T.sub.4) and a third (T.sub.6) transistor whose collector-emitter paths are arranged in series. The common point between the second and third transistors forms an output (5) of the power amplifier. The second transistor (T.sub.4) has its base connected to the collector of the first transistor (T.sub.1) and a control signal is applied to the base of the third transistor (T.sub.6) via a second resistor (R.sub.16). Furthermore, a first capacitor (C.sub.1) is arranged in parallel with the first resistor (R.sub.11) and the control signal is the input signal (E) or a fraction thereof. The power amplifier may comprise two cells whose first transistors (T.sub.1) have their emitters coupled to one another.

    Abstract translation: 一种功率放大器单元,包括由具有通过第一电阻器(R11)连接到第一电源电压端子的集电极的第一晶体管(T1)构成的反相输入放大器,以及包括第二(T4)和 其集电极 - 发射极路径串联布置的第三(T6)晶体管。 第二和第三晶体管之间的共同点形成功率放大器的输出(5)。 第二晶体管(T4)的基极连接到第一晶体管(T1)的集电极,并且经由第二电阻器(R16)将控制信号施加到第三晶体管(T6)的基极。 此外,第一电容器(C1)与第一电阻器(R11)并联布置,并且控制信号是输入信号(E)或其分数。 功率放大器可以包括两个单元,其第一晶体管(T1)的发射极彼此耦合。

    Bias circuitry for stacked transistor power amplifier stages
    3.
    发明授权
    Bias circuitry for stacked transistor power amplifier stages 失效
    用于堆叠晶体管功率放大器级的偏置电路

    公开(公告)号:US3887880A

    公开(公告)日:1975-06-03

    申请号:US36356373

    申请日:1973-05-24

    Applicant: RCA CORP

    CPC classification number: H03F1/307 H03F3/213 H03F3/3088

    Abstract: Stacked transistor power amplifier stages in an integratedcircuit quasi-linear amplifier are supplied quiescent bias currents which are in inverse proportion to their forward current gains. This permits selection of their quiescent collector currents to be at sufficiently low levels to reduce to low values both cross-over distortion and quiescent dissipation.

    Abstract translation: 集成电路准线性放大器中的堆叠晶体管功率放大器级提供与其正向电流增益成反比的静态偏置电流。 这允许其静态集电极电流的选择处于足够低的水平,以降低交叉失真和静态耗散的低值。

    Power drive circuit
    8.
    发明申请
    Power drive circuit 有权
    电源驱动电路

    公开(公告)号:US20010002801A1

    公开(公告)日:2001-06-07

    申请号:US09730097

    申请日:2000-12-05

    Applicant: ROHM CO., LTD.

    Inventor: Toshiro Okubo

    CPC classification number: H03F3/3088 H03F3/3081

    Abstract: A balanced transformer-less (BTL) power drive circuit comprises a push-pull type output transistor section connected with a main power supply PowVcc, and an input control section connected with an auxiliary power supply for providing the output transistor section with a control signal. The potential of the auxiliary power supply is selectively set equal to or above the supply potential of the main power supply, depending on the requirements for the dynamic range of the power chive circuit. In accord with the potential of the auxiliary power supply thus set, the output reference potential Vref is set to the medium of the dynamic range, thereby ensuring the linearity of the input-output characteristic of the drive circuit, irrespective of the selected level of the auxiliary power supply.

    Abstract translation: 平衡无变压器(BTL)功率驱动电路包括与主电源PowVcc连接的推挽型输出晶体管部分和与用于向输出晶体管部分提供控制信号的辅助电源连接的输入控制部分。 辅助电源的电位选择性地设定为等于或高于主电源的电源电位,这取决于对电源电路动态范围的要求。 根据这样设置的辅助电源的电位,将输出基准电位Vref设定为动态范围的介质,由此确保驱动电路的输入输出特性的线性,而与所选择的电平 辅助电源。

    Folded cascode operational amplifier with gain enhancing base current
compensation
    9.
    发明授权
    Folded cascode operational amplifier with gain enhancing base current compensation 失效
    具有增益增强基极电流补偿的折叠共源共栅运算放大器

    公开(公告)号:US5323121A

    公开(公告)日:1994-06-21

    申请号:US84004

    申请日:1993-06-29

    Inventor: James R. Butler

    Abstract: The gain of a folded cascode operational amplifier is enhanced by connecting the current circuits of added compensation transistors to supply the current circuits of pre-existing gain transistors. Changes in the current through the primary gain transistor resulting from a change in the output load produce approximately equal changes in the base currents of both the primary gain and primary compensation transistors. The change in the compensation transistor's base current is transmitted through the amplifier circuitry to supply the change in the gain transistor's base current, rather than forcing a change in the input voltage differential to supply this current. The differential input signal is thus less sensitive to changes in the output, resulting in higher transconductance and gain. Providing a similar compensation loop for a second gain transistor through the second compensation transistor produces a circuit balance that lowers both the circuit's offset voltage, and the temperature dependence of the offset voltage.

    Abstract translation: 通过连接添加的补偿晶体管的电流电路来提供折叠共源共栅运算放大器的增益,以提供预先存在的增益晶体管的电流电路。 由输出负载变化引起的通过初级增益晶体管的电流的变化在初级增益和初级补偿晶体管的基极电流中产生大致相等的变化。 补偿晶体管的基极电流的变化通过放大器电路传输,以提供增益晶体管的基极电流的变化,而不是强制输入电压差的变化来提供该电流。 因此,差分输入信号对输出的变化较不敏感,导致更高的跨导和增益。 通过第二补偿晶体管为第二增益晶体管提供类似的补偿环路产生电路平衡,其降低电路的偏移电压和偏移电压的温度依赖性。

    Operational amplifier with all NPN transistor output stage
    10.
    发明授权
    Operational amplifier with all NPN transistor output stage 失效
    具有所有NPN晶体管输出级的运算放大器

    公开(公告)号:US5285170A

    公开(公告)日:1994-02-08

    申请号:US983357

    申请日:1992-11-30

    CPC classification number: H03F3/3088

    Abstract: An operational amplifier achieves higher operating speed by using an all NPN transistor output drive stage. A control circuit in output drive stage receives an input signal and providing first and second control signals. The first and second control signals in turn drive first and second NPN output drive transistors arranged in a totem pole configuration between first and second power supply conductors.

    Abstract translation: 运算放大器通过使用全NPN晶体管输出驱动级实现更高的工作速度。 输出驱动级中的控制电路接收输入信号并提供第一和第二控制信号。 第一和第二控制信号又驱动以第一和第二电源导体之间的图腾柱结构排列的第一和第二NPN输出驱动晶体管。

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