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    Differential amplifier circuit
    2.
    发明授权
    Differential amplifier circuit 有权
    差分放大电路

    公开(公告)号：US6137350A

    公开(公告)日：2000-10-24

    申请号：US172861

    申请日：1998-10-15

    申请人： Tadashi Maeda

    发明人： Tadashi Maeda

    IPC分类号： H03F3/45 ,  G06G7/12

    CPC分类号： H03F3/45757 ,  H03F3/45385 ,  H03F2203/45702

    摘要： The average value of an input signal supplied to an input terminal is generated by an integrating circuit consisting of a series circuit of a capacitor, a constant-current source transistor, and a resistor. The average value is used as the reference voltage for the differential amplifier circuit. Further, to each of differential pair transistors the sources of which are commonly connected, other transistors are cascode connected, respectively. Supplied to each gate of the cascode connected transistors is a divisional voltage of the differential voltage between the average voltage from the integrating circuit and the circuit power supply voltage, which divisional voltage is obtained by a capacitive divider circuit.

    摘要翻译： 通过由电容器，恒流源晶体管和电阻器的串联电路组成的积分电路产生提供给输入端子的输入信号的平均值。 平均值用作差分放大器电路的参考电压。 此外，对于其源极共同连接的每个差分对晶体管，其他晶体管分别被共源共栅连接。 向共源共栅连接的晶体管的每个栅极提供的是积分电路的平均电压与电路电源电压之间的差分电压的分压，该分压是由电容分压电路获得的。

    Area efficient cascode driver circuit
    3.
    发明授权
    Area efficient cascode driver circuit 失效
    区域有效的共源共栅驱动电路

    公开(公告)号：US5087889A

    公开(公告)日：1992-02-11

    申请号：US658965

    申请日：1991-02-20

    申请人： James R. Butler

    发明人： James R. Butler

    IPC分类号： H01L27/085 ,  H03F3/45

    CPC分类号： H01L27/085 ,  H03F3/45385

    摘要： A JFET differential amplifier stage in which the gate-drain voltage of each input JFET is kept at least as great as the pinchoff voltage (V.sub.p), but preferably close to V.sub.p so as to reduce the effects of impact ionization and generation currents on the amplifier's input bias current. The input JFETs are cascoded with another pair of JFETs, and the gate-source circuits for the JFETs of each branch are connected in series with the gate-source circuit of an additional JFET between the gates and drains of the input JFETs. The additional JFET is supplied with a current that is substantially less than I.sub.DSS, and thus develops a significant portion of the necessary gate-drain voltages for the input JFETs. This enables a significant net reduction in the chip surface area occupied by the stage.

    摘要翻译： JFET差分放大器级，其中每个输入JFET的栅极 - 漏极电压保持至少与截止电压（Vp）一样大，但优选接近于Vp，以便减少放大器的电压和发生电流的影响 输入偏置电流。 输入JFET与另一对JFET串联，每个分支的JFET的栅极源电路与输入JFET的栅极和漏极之间的附加JFET的栅极 - 源极电路串联连接。 额外的JFET被提供有一个大大小于IDSS的电流，从而为输入JFET产生必要的栅 - 漏电压的很大一部分。 这使得能够显着地净化由平台占据的芯片表面积。

    Stability-compensated operational amplifier
    4.
    发明授权
    Stability-compensated operational amplifier 失效
    稳定运算放大器

    公开(公告)号：US5023567A

    公开(公告)日：1991-06-11

    申请号：US533890

    申请日：1990-06-06

    申请人： Timothy G. O'Shaughnessy ,  Mike Spaur

    发明人： Timothy G. O'Shaughnessy ,  Mike Spaur

    IPC分类号： H03F1/08 ,  H03F3/45

    CPC分类号： H03F3/45179 ,  H03F1/086 ,  H03F3/45381 ,  H03F3/45385 ,  H03F2203/45458 ,  H03F2203/45674 ,  H03F2203/45676

    摘要： A stability-compensated, integrated-circuit operational amplifier has an open-loop gain versus frequency characteristic which provides stable and accurate closed-loop operation in numerous overall circuits including a CMOS circuit for producing a precision current as a reference to a digital-to-analog converter. The operational amplifier comprises an inverting node and a non-inverting node, and CMOS circuitry defining two differential amplifiers. Each differential amplifier is connected to the inverting node and the non-inverting node. The first differential amplifier has an output node, and produces on the output node an output potential that defines an output signal having a magnitude that is a function of the magnitude of the difference between a first potential at the inverting node and a second potential at the non-inverting node. The second differential amplifier is also connected to the inverting node and the non-inverting node. The second differential amplifier produces a compensation signal. The operational amplifier further includes capacitive circuitry for coupling the compensation signal to the non-inverting node.

    摘要翻译： 稳定补偿的集成电路运算放大器具有开环增益与频率特性，其在许多总体电路中提供稳定和精确的闭环操作，包括用于产生精密电流的CMOS电路，作为数字 - 模拟转换器。 运算放大器包括反相节点和非反相节点，以及限定两个差分放大器的CMOS电路。 每个差分放大器连接到反相节点和非反相节点。 第一差分放大器具有输出节点，并且在输出节点上产生输出电位，该输出电位定义输出信号，该输出信号的幅度是反相节点处的第一电位和第二电位之间的差值的大小的函数 非反相节点。 第二差分放大器也连接到反相节点和非反相节点。 第二个差分放大器产生补偿信号。 运算放大器还包括用于将补偿信号耦合到非反相节点的电容电路。

    Apparatus and method for an input stage of an operational amplifier
    5.
    发明授权
    Apparatus and method for an input stage of an operational amplifier 失效
    运算放大器的输入级的装置和方法

    公开(公告)号：US5210505A

    公开(公告)日：1993-05-11

    申请号：US848863

    申请日：1992-03-10

    申请人： Dennis N. Eddlemon

    发明人： Dennis N. Eddlemon

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45179 ,  H03F3/45076 ,  H03F3/4508 ,  H03F3/45188 ,  H03F3/45385 ,  H03F3/45479 ,  H03F3/45735 ,  H03F2203/45674

    摘要： An operational amplifier input stage includes two transistors coupled as a differential amplifier to receive input signals. At least one transistor is stacked in a load circuit of each input transistor for the purpose of lowering the voltage across each transistor. In order to eliminate the effects of error currents resulting from conventional resistor self biasing of the stacked transistors, two nodes, to which the input transistors are coupled, are identified. According to a first embodiment, feedback circuits are coupled to each node and each feedback circuit maintains the coupled node at a voltage level established by the feedback apparatus of the operational amplifier. According to a second embodiment, a single feedback circuit controls the voltage at a first node and the same feedback circuit maintains the voltage level of a second node at a constant level. Either feedback circuit eliminates circuit drift and offset voltage changes resulting from changes in common mode and/or power supply voltages by eliminating the effects of resistive loading on the input stage components.

    摘要翻译： 运算放大器输入级包括耦合作为差分放大器以接收输入信号的两个晶体管。 为了降低每个晶体管上的电压，至少一个晶体管堆叠在每个输入晶体管的负载电路中。 为了消除由堆叠晶体管的常规电阻器自偏压引起的误差电流的影响，识别输入晶体管耦合到的两个节点。 根据第一实施例，反馈电路耦合到每个节点，并且每个反馈电路将耦合节点维持在由运算放大器的反馈装置建立的电压电平。 根据第二实施例，单个反馈电路控制第一节点处的电压，并且相同的反馈电路将第二节点的电压电平维持在恒定水平。 反馈电路通过消除输入级组件上的电阻负载的影响，消除了由共模和/或电源电压变化引起的电路漂移和偏移电压变化。

    Apparatus and method for an input stage of an operational amplifier
    6.
    发明授权
    Apparatus and method for an input stage of an operational amplifier 失效
    运算放大器的输入级的装置和方法

    公开(公告)号：US5142243A

    公开(公告)日：1992-08-25

    申请号：US618388

    申请日：1990-12-19

    申请人： Dennis N. Eddlemon

    发明人： Dennis N. Eddlemon

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45179 ,  H03F3/4508 ,  H03F3/45188 ,  H03F3/45385 ,  H03F3/45735 ,  H03F2203/45674

    摘要： An operational amplifier input stage includes two transistors coupled as a differential amplifier to receive input signals. At least one transistor is stacked in a load circuit of each input transistor for the purpose of lowering the voltage across each transistor. In order to eliminate the effects of error currents resulting from conventional resistor self biasing of the stacked transistors, two nodes, to which the input transistors are coupled, are identified. A feedback circuit is coupled to each node and each feedback circuit maintains the coupled node at a voltage level established by the feedback apparatus of the operational amplifier. The disclosed circuit eliminates circuit drift and offset voltages resulting from changes in common mode and/or power supply voltages by eliminating the effects of resistive loading on the input stage components.

    摘要翻译： 运算放大器输入级包括耦合作为差分放大器以接收输入信号的两个晶体管。 为了降低每个晶体管上的电压，至少一个晶体管堆叠在每个输入晶体管的负载电路中。 为了消除由堆叠晶体管的常规电阻器自偏压引起的误差电流的影响，识别输入晶体管耦合到的两个节点。 反馈电路耦合到每个节点，并且每个反馈电路将耦合节点维持在由运算放大器的反馈装置建立的电压电平。 所公开的电路通过消除对输入级组件的电阻负载的影响而消除由共模和/或电源电压的变化引起的电路漂移和偏移电压。

    Differential amplifying circuit operable at high speed
    7.
    发明授权
    Differential amplifying circuit operable at high speed 失效
    差速放大电路可在高速运行

    公开(公告)号：US5065111A

    公开(公告)日：1991-11-12

    申请号：US535029

    申请日：1990-06-08

    申请人： Akinori Tsukuda ,  Masahisa Nemoto ,  Haruo Mori

    发明人： Akinori Tsukuda ,  Masahisa Nemoto ,  Haruo Mori

    IPC分类号： H03K19/0952 ,  H03F3/45

    CPC分类号： H03F3/45385 ,  H03F2203/45024 ,  H03F2203/45186 ,  H03F2203/45244 ,  H03F2203/45641

    摘要： A differential amplifying circuit includes a differential input portion, a load portion, a switching portion, and a constant current source. The differential input portion is connected to the constant current source, and includes a pair of field effect transistors (FETs), with one having a gate for receiving an input voltage, a source connected to the current source and a drain connected to a first node, and the other having a gate for receiving a reference voltage, a source connected to the current source and a drain connected to a second node. The load portion includes a pair of FETs, with one having a drain connected to a first power source and a source connected to a first output terminal, and the other having a drain connected to the first power source and a source connected to a second output terminal. The switching portion includes a pair of FETs, with one having a source connected to the first output terminal, and the other having a source connected to the second output terminal. The pair of FETs of the load portion respond to the potentials of the first and second nodes, respectively, so that the switching portion can perform a high speed switching operation.