公开(公告)号：US20240333281A1

公开(公告)日：2024-10-03

申请号：US18598920

申请日：2024-03-07

Applicant: STMicroelectronics International N.V.

Inventor： Manoj Kumar TIWARI ,  Sandeep KAUSHIK ,  Zia PARVEEN

IPC: H03K17/56

CPC classification number: H03K17/56

Abstract: Provided is a circuit that sets a voltage of a failsafe node. The circuit includes a first voltage setting transistor configured to operate in a conductive state to set a voltage of the failsafe node to a supply voltage of a supply voltage node. The circuit includes first and second control transistors configured to control the first voltage setting transistor to operate in the conductive state in response to both the supply voltage and a pad node voltage of a pad node corresponding to logical one and control the first voltage setting transistor to operate in a nonconductive state in response to one of the supply voltage or the pad node voltage corresponding to the logical one and another one of the supply voltage or the pad node voltage corresponding to logical zero.

公开(公告)号：US20240045458A1

公开(公告)日：2024-02-08

申请号：US18356818

申请日：2023-07-21

Applicant: STMicroelectronics International N.V.

Inventor： Zubair KHAN ,  Sandeep KAUSHIK

IPC: G05F1/575 ,  G05F1/46

CPC classification number: G05F1/575 ,  G05F1/468

Abstract: Provided are techniques for detecting a short circuit fault at an output of a regulator and protecting the regulator from the short circuit fault. An error amplifier receives a reference voltage and a feedback voltage and compares comparing the reference voltage with the feedback voltage for driving a power transistor of the regulator. A modification stage compares an output voltage of the voltage regulator with a fault reference voltage and in response to determining that the output voltage of the voltage regulator is less than the fault reference voltage, drives the power transistor using an internal node of the error amplifier by changing states of a first switch and a second switch and supplies the reference voltage to both the first and second inputs of the error amplifier by changing states of a third switch and a fourth switch.

公开(公告)号：US20230275586A1

公开(公告)日：2023-08-31

申请号：US18098421

申请日：2023-01-18

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep KAUSHIK ,  Paras GARG

IPC: H03K19/0185 ,  H03K17/687 ,  H03K19/017

CPC classification number: H03K19/018514 ,  H03K19/018585 ,  H03K17/6871 ,  H03K19/01707

Abstract: A Low Voltage Differential Signaling (LVDS) transmitter includes driver circuit with a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between a first node and first output. The second transistor is coupled between the first node and a second output. The third transistor is coupled between the first output and a second node. The fourth transistor is coupled between the second output and the second node. The first resistor is coupled between the first output and a common mode node. The second resistor is coupled between the second output and the common mode node. A pre-driver circuit generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal. A controlled timing delay is applied to the timing of logic state transistors for the control signals.

公开(公告)号：US20250125804A1

公开(公告)日：2025-04-17

申请号：US18988037

申请日：2024-12-19

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep KAUSHIK ,  Paras GARG

IPC: H03K19/0185 ,  H03K17/687 ,  H03K19/017

Abstract: A Low Voltage Differential Signaling (LVDS) transmitter includes driver circuit with a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between a first node and first output. The second transistor is coupled between the first node and a second output. The third transistor is coupled between the first output and a second node. The fourth transistor is coupled between the second output and the second node. The first resistor is coupled between the first output and a common mode node. The second resistor is coupled between the second output and the common mode node. A pre-driver circuit generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal. A controlled timing delay is applied to the timing of logic state transistors for the control signals.

公开(公告)号：US20250117350A1

公开(公告)日：2025-04-10

申请号：US18788862

申请日：2024-07-30

Applicant: STMicroelectronics International N.V.

Inventor： Manoj Kumar TIWARI ,  Paras GARG ,  Sandeep KAUSHIK ,  Adarsh Kumar SINGH

IPC: G06F13/40 ,  G06F13/42 ,  H03K17/687

Abstract: Systems, apparatuses, and methods for serial peripheral interfaces are provided, particularly for PVT compensated serial peripheral interfaces with slow transition serial interface IO transmitter with reduced delay. The serial peripheral interfaces may include driver circuitry, pre-driver circuitry, PVT compensated current sink circuitry, and PVT compensated current source circuit. The PVT compensated current sink circuitry and PVT compensated current source circuit may generate and transmit signals compensating for PVT to the pre-driver circuitry, which may generate and transmit signals controlling IO data signals generated by the driver circuitry. The IO data signals generated may be compensated for process, voltage, and temperature. The compensation may provide IO data signals with slower transition times and with reduced delays.

公开(公告)号：US20210067159A1

公开(公告)日：2021-03-04

申请号：US16999813

申请日：2020-08-21

Applicant: STMicroelectronics International N.V.

Inventor： Paras GARG ,  Ankit AGRAWAL ,  Sandeep KAUSHIK

IPC: H03K17/687 ,  H03K19/0185

Abstract: In various embodiments, the present disclosure provides low-voltage differential signaling (LVDS) receiver circuits, electronic devices, and methods. In one embodiment, a LVDS receiver includes an input differential pair of transistors that receive a differential input signal. The input differential pair includes a first NMOS transistor that receives a first input signal and a second NMOS transistor that receives a second input signal. A third NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the first NMOS transistor, and a fourth NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the second NMOS transistor. A first level shifter is coupled to a gate of the third NMOS transistor, and a second level shifter is coupled to a gate of the fourth NMOS transistor.