公开(公告)号：US4547790A

公开(公告)日：1985-10-15

申请号：US637704

申请日：1984-08-06

申请人： Hideharu Egawa

发明人： Hideharu Egawa

IPC分类号： H01L21/86 ,  H01L27/092 ,  H01L27/12 ,  H03K3/356 ,  H03K19/0944 ,  H03K19/0948 ,  H01L29/06 ,  H01L27/02 ,  H01L27/04 ,  H01L29/78

CPC分类号： H01L27/12 ,  H01L21/86 ,  H01L27/092 ,  H03K19/09446 ,  H03K19/09487 ,  H03K3/356 ,  Y10S257/903

摘要： A semiconductor device includes p- and n-type semiconductor layers formed on an insulating substrate and gate electrodes selectively and insulatively formed over the respective p- and n-type semiconductor layers and forming D-type MOS transistors. In this semiconductor device, the p- and n-type semiconductor layers are made in contact with each other, and negative and positive power supply terminals which are respectively set at negative and positive potentials are respectively connected to the p- and n-type semiconductor layers thereby to electrically isolate the p-type and n-type semiconductor layers from each other.

公开(公告)号：US20060181313A1

公开(公告)日：2006-08-17

申请号：US11269610

申请日：2005-11-09

申请人： Akira Akahori

发明人： Akira Akahori

IPC分类号： H03K19/094

CPC分类号： H03K19/1737 ,  H03K19/09446

摘要： An input inverter section inverts a plurality of input signals to generate complementary signals and supplies signals complementary to these input signals to a logic circuit network. The logic circuit network comprises a plurality of pairs of depletion type NMOSs (NDMOSs) whose conducting states are respectively controlled on a complementary basis by the supplied signals. Since each of the NDMOSs has a threshold voltage set negative, a drain current flows even if its gate voltage is 0V, and hence it is not brought into a complete off state. It is therefore possible to speed up a change from an off state to an on state and raise a signal of an “H” level at a node from which a signal indicative of the result of logical operations is outputted, to a potential identical to a power supply potential. The signal at the node is outputted from an output buffer section as an output signal.

摘要翻译： 输入反相器部分反转多个输入信号以产生互补信号，并将与这些输入信号互补的信号提供给逻辑电路网络。 逻辑电路网络包括多对耗尽型NMOS（NDMOS），其通过所提供的信号在互补的基础上分别控制其导通状态。 由于每个NDMOS的阈值电压设置为负值，所以即使栅极电压为0V，漏极电流也流动，因此不会进入完全关闭状态。 因此，可以将从关闭状态的变化加速到接通状态，并且在表示逻辑运算结果的信号的输出的节点将“H”电平的信号提升到与 供电潜力 节点处的信号作为输出信号从输出缓冲器部分输出。

公开(公告)号：US4677325A

公开(公告)日：1987-06-30

申请号：US872354

申请日：1986-06-09

申请人： Josef Einzinger ,  Christine Fellinger ,  Ludwig Leipold ,  Jenoe Tihanyi ,  Roland Weber

发明人： Josef Einzinger ,  Christine Fellinger ,  Ludwig Leipold ,  Jenoe Tihanyi ,  Roland Weber

IPC分类号： H03K17/687 ,  H03K19/0944 ,  H03K19/0948 ,  H03K17/16 ,  H03K19/094 ,  H03K19/20

CPC分类号： H03K17/6872 ,  H03K19/09446 ,  H03K19/0948

摘要： A switching circuit includes two series-connected MOSFET (1, 6) complementing one another, which are interconnected at the drain terminal of each device. The gate terminal of the MOSFET that is grounded is connected to a control input terminal (E). This gate terminal is also connected to the source terminal of a depletion FET (7). The drain terminal of the depletion FET (7) is connected to the gate terminal of the second MOSFET (6) and, in turn, is connected via a resistor (8) to a voltage source (+U). The gate terminal of the depletion FET (7) is grounded. The load (5) is then connected to the drain side of the complementary MOSFET. When the switch is in a blocking condition, the cross current is thus prevented from flowing; and the FET connected to voltage can be completely activated.

摘要翻译： 开关电路包括彼此互补的两个串联连接的MOSFET（1,6），它们在每个器件的漏极端子处互连。 接地的MOSFET的栅极端子连接到控制输入端子（E）。 该栅极端子也连接到耗尽FET（7）的源极端子。 耗尽FET（7）的漏极端子连接到第二MOSFET（6）的栅极端子，并且又通过电阻器（8）连接到电压源（+ U）。 耗尽FET（7）的栅极端子接地。 负载（5）然后连接到互补MOSFET的漏极侧。 当开关处于阻塞状态时，防止交叉电流流动; 连接到电压的FET可以被完全激活。

公开(公告)号：US4547681A

公开(公告)日：1985-10-15

申请号：US624815

申请日：1984-06-26

申请人： Hideharu Egawa

发明人： Hideharu Egawa

IPC分类号： H01L21/86 ,  H01L27/092 ,  H01L27/12 ,  H03K3/356 ,  H03K19/0944 ,  H03K19/0948 ,  H03L1/00 ,  H03K17/14 ,  H03K19/003 ,  H03L5/00

CPC分类号： H01L27/12 ,  H01L21/86 ,  H01L27/092 ,  H03K19/09446 ,  H03K19/09487 ,  H03K3/356 ,  Y10S257/903

摘要： A semiconductor device includes p- and n-type semiconductor layers formed on an insulating substrate and gate electrodes selectively and insulatively formed over the respective p- and n-type semiconductor layers and forming D-type MOS transistors. In this semiconductor device, the p- and n-type semiconductor layers are made in contact with each other, and negative and positive power supply terminals which are respectively set at negative and positive potentials are respectively connected to the p- and n-type semiconductor layers thereby to electrically isolate the p-type and n-type semiconductor layers from each other.

摘要翻译： 半导体器件包括在绝缘衬底上形成的p型和n型半导体层，并且在各个p型和n型半导体层上选择性地并且绝对地形成栅极，并形成D型MOS晶体管。 在该半导体器件中，使p型和n型半导体层彼此接触，分别设定为负电位和正电位的负极和正电源端分别连接到p型和n型半导体 从而将p型和n型半导体层彼此电隔离。

公开(公告)号：US4395645A

公开(公告)日：1983-07-26

申请号：US213533

申请日：1980-12-05

申请人： Joseph Pernyeszi

发明人： Joseph Pernyeszi

IPC分类号： H03K19/0175 ,  H03K19/0185 ,  H03K19/0944 ,  H03K19/094 ,  H03K3/353 ,  H03K17/687 ,  H03K19/20

CPC分类号： H03K19/018507 ,  H03K19/09445 ,  H03K19/09446

摘要： The inverter buffer circuit disclosed includes two transistorized circuits each coupled to an input circuit and an output circuit capable of carrying high current and providing full output swing between a high voltage or binary "1" and a low voltage or binary "0". Each of the two circuits include a first enhancement field effect transistor having its drain electrode connected to a drain voltage and operating as a source follower, a first depletion field effect transistor having its drain electrode and source electrode connected to back bias acting as a load for the first enhancement transistor, second and third enhancement field effect transistors having their source electrodes coupled to the back bias and interconnected to form a flip-flop controlled by the first enhancement transistor and a second depletion field effect transistor having its drain electrode coupled to the drain voltage and acting as the load for the flip-flop. The output circuit includes two depletion field effect transistors connected in series between the drain voltage and source voltage with the gate electrodes thereof connected to a different one of the two flip-flops and an output terminal coupled to the series connection between the two depletion transistors. Three embodiments of the input circuit are disclosed.

摘要翻译： 所公开的逆变器缓冲电路包括两个晶体管电路，每个都耦合到输入电路和能够承载高电流并在高电压或二进制“1”与低电压或二进制“0”之间提供全输出摆幅的输出电路。 两个电路中的每一个包括第一增强场效应晶体管，其第一增强场效应晶体管的漏极连接到漏极电压并用作源极跟随器，第一耗尽场效应晶体管的漏极电极和源电极连接到反偏压，用作负载 第一增强型晶体管，第二和第三增强场效应晶体管的源极耦合到背偏置并互连，以形成由第一增强晶体管控制的触发器和第二耗尽场效应晶体管，其漏极连接到漏极 并作为触发器的负载。 输出电路包括串联连接在漏极电压和源极电压之间的两个耗尽场效应晶体管，其栅电极连接到两个触发器中的不同一个，以及耦合到两个耗尽晶体管之间的串联连接的输出端子。 公开了输入电路的三个实施例。