公开(公告)号：US06275405B1

公开(公告)日：2001-08-14

申请号：US09458217

申请日：1999-12-09

申请人： Joseph Pernyeszi

发明人： Joseph Pernyeszi

IPC分类号： H02M506

CPC分类号： H02M5/14 ,  H02P27/024

摘要： A phase converter for converting single-phase power to three-phase power, wherein the single-phase power is provided at a first and a second single-phase power terminal and the three-phase power is provided to a first, a second and a third three-phase power terminal, the phase converter comprising: a first power transfer means for coupling the first single-phase power terminal to the first three-phase power terminal; a second power transfer means for coupling the second single-phase power terminal to the second three-phase power terminal; and an inverter coupled to receive power from the first and second single-phase power terminals. The inverter provides power to the third three-phase power terminal and a neutral output by phase shifting its input power by ninety degrees.

摘要翻译： 一种用于将单相电力转换为三相电力的相位转换器，其中单相电力被提供在第一和第二单相电源端子处，并且三相电力被提供给第一，第二和第二相 第三三相电源端子，所述相位转换器包括：用于将所述第一单相电源端子耦合到所述第一三相电力端子的第一电力传送装置; 用于将第二单相电源端子耦合到第二三相电源端子的第二电力传送装置; 以及耦合以从第一和第二单相电源端子接收电力的逆变器。 逆变器通过将其输入功率相移90度来向第三个三相电源端子和中性点输出提供电源。

公开(公告)号：US4453134A

公开(公告)日：1984-06-05

申请号：US400199

申请日：1982-07-20

申请人： Joseph Pernyeszi

发明人： Joseph Pernyeszi

IPC分类号： H03F3/30 ,  H03F3/45 ,  H03F3/26

CPC分类号： H03F3/3071 ,  H03F3/45071

摘要： An operational amplifier is disclosed which is capable of handling input voltages in excess of 200 volts, comprising at least in the input stage thereof a plurality of low voltage transistors including at least a pair of low voltage lateral PNP transistors each having two collectors. These lateral PNP transistors act as level shifters for the amplifier and also a bias arrangement for the input stage. A single high voltage lateral PNP is in the signal path providing the lowest pole in the transfer function and to compensate for low to medium loop gains.

摘要翻译： 公开了能够处理超过200伏的输入电压的运算放大器，其至少在其输入级中包括多个低压晶体管，其包括至少一对具有两个集电极的低压侧PNP晶体管。 这些横向PNP晶体管用作放大器的电平移位器，并且还用作输入级的偏置装置。 单个高电压横向PNP位于信号路径中，提供传递函数中的最低极点，并补偿低至中等环路增益。

公开(公告)号：US09438123B2

公开(公告)日：2016-09-06

申请号：US14854768

申请日：2015-09-15

申请人： Joseph Pernyeszi

发明人： Joseph Pernyeszi

IPC分类号： H05B33/08 ,  H02M3/335

CPC分类号： H02M3/33507 ,  H02M3/158 ,  H02M3/3372 ,  H02M3/3376 ,  H02M2001/0058 ,  H05B33/0815 ,  Y02B70/1425 ,  Y02B70/1433 ,  Y02B70/1491

摘要： Push-pull circuits are described that are suitable for the driving of LEDs and that reduce the voltage stress on the switching transistors that is caused by the output transformer. The push-pull arrangement caters to reducing the size of the transformer as it eliminates the DC magnetic bias of the transformer core and it also caters to the integration of the semiconductor content of the circuit requiring only low side DMOS to be implemented in the monolithic, junction isolated process.

摘要翻译： 描述了适用于驱动LED并且降低由输出变压器引起的开关晶体管上的电压应力的推挽电路。 推拉装置可以减轻变压器的尺寸，因为它消除了变压器磁芯的直流磁偏置，并且还适用于仅需要低端DMOS的电路的半导体内容的集成，可以实现在单片， 连接隔离过程。

公开(公告)号：US20160163791A1

公开(公告)日：2016-06-09

申请号：US14959286

申请日：2015-12-04

申请人： Joseph Pernyeszi

发明人： Joseph Pernyeszi

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/0634 ,  H01L21/76237 ,  H01L29/0692 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/7816

摘要： A high voltage DMOS half-bridge output for various DC to DC converters on a monolithic, junction isolated wafer is presented. A high-side lateral DMOS transistor is based on the epi extension diffusion and a five layer RESURF structure. The five layers are made possible by the epi extension diffusion which is formed by a suitable n-type dopant diffused into a p-type substrate and it is the same polarity as the epi. The five layers, starting with the p-type substrate, are the substrate, the n-type epi extension diffusion, a p-type buried layer, the n-type epi and a shallow p-type layer at the top of the epi. The epi extension is also used to shape the electric field by a specific lateral distribution and make the lateral and vertical electric fields to be the smoothest to avoid electric field induced breakdown in the silicon or oxide layers above the silicon.

摘要翻译： 提出了一种用于单片，隔离晶圆上的各种DC-DC转换器的高压DMOS半桥输出。 高侧横向DMOS晶体管基于外延扩展扩散和五层RESURF结构。 通过由扩散到p型衬底中的合适的n型掺杂物形成的外延延伸扩散使得五层成为可能，并且它与epi具有相同的极性。 从p型衬底开始的五层是epi顶部的衬底，n型epi延伸扩散，p型掩埋层，n型epi和浅p型层。 外延扩展还用于通过特定的横向分布来形成电场，并且使得横向和垂直电场是最平滑的，以避免在硅上方的硅或氧化物层中的电场引起的击穿。

公开(公告)号：US4864126A

公开(公告)日：1989-09-05

申请号：US207809

申请日：1988-06-17

申请人： Michael D. Walters ,  Joseph Pernyeszi ,  John F. Petrilla

发明人： Michael D. Walters ,  Joseph Pernyeszi ,  John F. Petrilla

IPC分类号： H03K17/78 ,  H03K17/042 ,  H03K17/16 ,  H03K17/687 ,  H03K17/785

CPC分类号： H03K17/6874 ,  H03K17/04206 ,  H03K17/162 ,  H03K17/165 ,  H03K17/785

摘要： A solid state relay uses an optically controlled shunt and series enhancement circuit between a photodiode array and an output device to provide enhanced turn-off and transient immunity characteristics. A Faraday shield may be used to cover optically active components and to provide protection against false turn-on and turn-off caused by the transients.

公开(公告)号：US4395645A

公开(公告)日：1983-07-26

申请号：US213533

申请日：1980-12-05

申请人： Joseph Pernyeszi

发明人： Joseph Pernyeszi

IPC分类号： H03K19/0175 ,  H03K19/0185 ,  H03K19/0944 ,  H03K19/094 ,  H03K3/353 ,  H03K17/687 ,  H03K19/20

CPC分类号： H03K19/018507 ,  H03K19/09445 ,  H03K19/09446

摘要： The inverter buffer circuit disclosed includes two transistorized circuits each coupled to an input circuit and an output circuit capable of carrying high current and providing full output swing between a high voltage or binary "1" and a low voltage or binary "0". Each of the two circuits include a first enhancement field effect transistor having its drain electrode connected to a drain voltage and operating as a source follower, a first depletion field effect transistor having its drain electrode and source electrode connected to back bias acting as a load for the first enhancement transistor, second and third enhancement field effect transistors having their source electrodes coupled to the back bias and interconnected to form a flip-flop controlled by the first enhancement transistor and a second depletion field effect transistor having its drain electrode coupled to the drain voltage and acting as the load for the flip-flop. The output circuit includes two depletion field effect transistors connected in series between the drain voltage and source voltage with the gate electrodes thereof connected to a different one of the two flip-flops and an output terminal coupled to the series connection between the two depletion transistors. Three embodiments of the input circuit are disclosed.

摘要翻译： 所公开的逆变器缓冲电路包括两个晶体管电路，每个都耦合到输入电路和能够承载高电流并在高电压或二进制“1”与低电压或二进制“0”之间提供全输出摆幅的输出电路。 两个电路中的每一个包括第一增强场效应晶体管，其第一增强场效应晶体管的漏极连接到漏极电压并用作源极跟随器，第一耗尽场效应晶体管的漏极电极和源电极连接到反偏压，用作负载 第一增强型晶体管，第二和第三增强场效应晶体管的源极耦合到背偏置并互连，以形成由第一增强晶体管控制的触发器和第二耗尽场效应晶体管，其漏极连接到漏极 并作为触发器的负载。 输出电路包括串联连接在漏极电压和源极电压之间的两个耗尽场效应晶体管，其栅电极连接到两个触发器中的不同一个，以及耦合到两个耗尽晶体管之间的串联连接的输出端子。 公开了输入电路的三个实施例。

公开(公告)号：US4333133A

公开(公告)日：1982-06-01

申请号：US189470

申请日：1980-09-22

申请人： Joseph Pernyeszi

发明人： Joseph Pernyeszi

IPC分类号： H02M3/156 ,  H02M3/00 ,  H02P13/18

CPC分类号： H02M3/156

摘要： A circuit arrangement to provide a fixed voltage source in series with an arbitrarily chosen impedance of any magnitude and phase shift having very low power dissipation and capable of being fabricated on silicon integrated chips is disclosed. The circuit arrangement includes a sensing resistor to sense the output current of a power converter which is amplified and fed back with an appropriate phase shift to control the output voltage of the converter. An independent control signal may be combined with the fed back voltage to change the chosen impedance to another type of impedance.

摘要翻译： 公开了一种提供固定电压源的电路装置，其具有任意幅度和相移的任意选择的阻抗，该阻抗具有非常低的功率消耗并能够制造在硅集成芯片上。 电路装置包括用于检测功率转换器的输出电流的感测电阻器，其被放大并用适当的相移反馈以控制转换器的输出电压。 独立的控制信号可以与反馈电压组合以将所选择的阻抗改变成另一种类型的阻抗。

公开(公告)号：US09570547B2

公开(公告)日：2017-02-14

申请号：US14959286

申请日：2015-12-04

申请人： Joseph Pernyeszi

发明人： Joseph Pernyeszi

IPC分类号： H01L29/94 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/762

CPC分类号： H01L29/0634 ,  H01L21/76237 ,  H01L29/0692 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/7816

摘要： A high voltage DMOS half-bridge output for various DC to DC converters on a monolithic, junction isolated wafer is presented. A high-side lateral DMOS transistor is based on the epi extension diffusion and a five layer RESURF structure. The five layers are made possible by the epi extension diffusion which is formed by a suitable n-type dopant diffused into a p-type substrate and it is the same polarity as the epi. The five layers, starting with the p-type substrate, are the substrate, the n-type epi extension diffusion, a p-type buried layer, the n-type epi and a shallow p-type layer at the top of the epi. The epi extension is also used to shape the electric field by a specific lateral distribution and make the lateral and vertical electric fields to be the smoothest to avoid electric field induced breakdown in the silicon or oxide layers above the silicon.

摘要翻译： 提出了一种用于单片，隔离晶圆上的各种DC-DC转换器的高压DMOS半桥输出。 高侧横向DMOS晶体管基于外延扩展扩散和五层RESURF结构。 通过由扩散到p型衬底中的合适的n型掺杂物形成的外延延伸扩散使得五层成为可能，并且它与epi具有相同的极性。 从p型衬底开始的五层是epi顶部的衬底，n型epi延伸扩散，p型掩埋层，n型epi和浅p型层。 外延扩展还用于通过特定的横向分布来形成电场，并且使得横向和垂直电场是最平滑的，以避免在硅上方的硅或氧化物层中的电场引起的击穿。

公开(公告)号：US5847593A

公开(公告)日：1998-12-08

申请号：US822742

申请日：1997-03-25

申请人： Joseph Pernyeszi

发明人： Joseph Pernyeszi

IPC分类号： G05F1/67 ,  H03K17/785 ,  H03K17/60

CPC分类号： H03K17/785 ,  G05F1/67 ,  Y02E10/58

摘要： A circuit for discharging of a photovoltaic power source has a first and a second terminal and the circuit comprises a discharge circuit which is connected between the first and second terminal of the power source which comprises a controllable current source which is controlled by a band gap reference.

摘要翻译： 用于放电光伏电源的电路具有第一和第二端子，并且该电路包括连接在电源的第一和第二端子之间的放电电路，其包括由带隙基准控制的可控电流源 。

公开(公告)号：US4902901A

公开(公告)日：1990-02-20

申请号：US338872

申请日：1989-04-14

申请人： Joseph Pernyeszi

发明人： Joseph Pernyeszi

IPC分类号： H03K17/78 ,  H03K17/042 ,  H03K17/687 ,  H03K17/785

CPC分类号： H03K17/785 ,  H03K17/04206 ,  H03K17/6874

摘要： A high-power solid state relay uses optically-controlled shunt and series solid state switches between a photodiode array and an output device to provide enhanced turn-off and transient immunity characteristics and an optically-controlled charging network connected to the switched load to enhance the turn-on characteristics of the relay.