公开(公告)号：US4883986A

公开(公告)日：1989-11-28

申请号：US378266

申请日：1982-05-14

申请人： Hideharu Egawa ,  Yasoji Suzuki

发明人： Hideharu Egawa ,  Yasoji Suzuki

IPC分类号： H01L27/092 ,  H01L27/12 ,  H03K19/0948

CPC分类号： H03K19/0948 ,  H01L27/092 ,  H01L27/12

摘要： A semiconductor circuit has a power source terminal set at a positive potential, a reference potential terminal set at a reference potential, a first MOS transistor whose current path is connected between the power source terminal and an output terminal, and a second MOS transistor whose current path is connected between the output terminal and the reference potential terminal. The gates of the first and second MOS transistors are commonly connected to an input terminal. The first and second MOS transistors are respectively n- and p-channel MOS transistors.

摘要翻译： 半导体电路具有设置为正电位的电源端子，设定在基准电位的基准电位端子，电流路径连接在电源端子与输出端子之间的第一MOS晶体管和电流端子的电流端子 路径连接在输出端子和参考电位端子之间。 第一和第二MOS晶体管的栅极通常连接到输入端。 第一和第二MOS晶体管分别是n沟道和p沟道MOS晶体管。

公开(公告)号：US4547790A

公开(公告)日：1985-10-15

申请号：US637704

申请日：1984-08-06

申请人： Hideharu Egawa

发明人： Hideharu Egawa

IPC分类号： H01L21/86 ,  H01L27/092 ,  H01L27/12 ,  H03K3/356 ,  H03K19/0944 ,  H03K19/0948 ,  H01L29/06 ,  H01L27/02 ,  H01L27/04 ,  H01L29/78

CPC分类号： H01L27/12 ,  H01L21/86 ,  H01L27/092 ,  H03K19/09446 ,  H03K19/09487 ,  H03K3/356 ,  Y10S257/903

摘要： A semiconductor device includes p- and n-type semiconductor layers formed on an insulating substrate and gate electrodes selectively and insulatively formed over the respective p- and n-type semiconductor layers and forming D-type MOS transistors. In this semiconductor device, the p- and n-type semiconductor layers are made in contact with each other, and negative and positive power supply terminals which are respectively set at negative and positive potentials are respectively connected to the p- and n-type semiconductor layers thereby to electrically isolate the p-type and n-type semiconductor layers from each other.

公开(公告)号：US4488674A

公开(公告)日：1984-12-18

申请号：US423283

申请日：1982-09-24

申请人： Hideharu Egawa ,  Katsuya Okumura

发明人： Hideharu Egawa ,  Katsuya Okumura

IPC分类号： H01L21/60 ,  H01L23/49

CPC分类号： H01L24/85 ,  H01L24/745 ,  H01L24/78 ,  H01L2224/05553 ,  H01L2224/43822 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/745 ,  H01L2224/78 ,  H01L2224/8502 ,  H01L2224/851 ,  H01L2224/85205 ,  H01L24/45 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  Y10T29/49162

摘要： The invention provides a bonding wire which prevents electric short-circuiting even if it comes into contact with another bonding wire, a bonding method using the same, and a semiconductor device including the same. The bonding wire comprises a core wire made of a metal and an insulating film which surrounds it. The insulating film is eliminated from the ends of the bonding wire by thermal decomposition and scattering, while simultaneously each end of the bonding wire is connected to a bonding pad of the semiconductor device or to a lead frame. In the semiconductor device, the bonding pads are respectively connected to lead frames by means of the bonding wires.

摘要翻译： 本发明提供了即使与另一个接合线接触也防止电气短路的接合线，使用该接合线的接合方法以及包括该接合线的半导体器件。 接合线包括由金属制成的芯线和围绕它的绝缘膜。 通过热分解和散射，从接合线的端部除去绝缘膜，同时将接合线的每个端部连接到半导体器件的接合焊盘或引线框架。 在半导体器件中，接合焊盘通过接合线分别连接到引线框架。

公开(公告)号：US4209830A

公开(公告)日：1980-06-24

申请号：US932400

申请日：1978-08-09

申请人： Yoshiaki Arimura ,  Hideharu Egawa ,  Yasoji Suzuki

发明人： Yoshiaki Arimura ,  Hideharu Egawa ,  Yasoji Suzuki

IPC分类号： G06T7/00 ,  G06F15/46

CPC分类号： G06T7/0042

摘要： A position and direction sensing mark is formed on an integrated circuit pellet formed with a prescribed electrode pattern. The position and direction sensing mark comprises a plurality of strips which are extended in a direction different from that in which the electrode pattern is extended and are arranged in turn at prescribed intervals in a direction intersecting the different direction at right angles thereto.

摘要翻译： 位置和方向检测标记形成在形成有规定电极图案的集成电路芯片上。 位置和方向检测标记包括沿与电极图案延伸的方向不同的方向延伸的多个条带，并且在与其不同的方向交叉的方向上以规定的间隔依次布置。

公开(公告)号：US5061983A

公开(公告)日：1991-10-29

申请号：US318411

申请日：1989-02-28

申请人： Hideharu Egawa ,  Yoshio Nishi ,  Kenji Maeguchi

发明人： Hideharu Egawa ,  Yoshio Nishi ,  Kenji Maeguchi

IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L23/532 ,  H01L27/12 ,  H01L29/43

CPC分类号： H01L23/53271 ,  H01L27/12 ,  H01L2924/0002

摘要： A method for manufacturing a semiconductor device that includes p- and n-type regions formed on an insulating substrate, and an interconnection layer electrically coupled with these p- and n-type regions. The interconnection layer is an n-type polycrystalline silicon layer which is electrically coupled with the p- and n-type regions through a metal silicide film formed between the interconnection layer and the p- and n-type regions.

摘要翻译： 一种制造半导体器件的方法，该半导体器件包括形成在绝缘衬底上的p型和n型区域，以及与这些p型和n型区域电耦合的互连层。 互连层是通过在互连层和p型区域和n型区域之间形成的金属硅化物膜与p型区域和n型区域电耦合的n型多晶硅层。

公开(公告)号：US4547681A

公开(公告)日：1985-10-15

申请号：US624815

申请日：1984-06-26

申请人： Hideharu Egawa

发明人： Hideharu Egawa

IPC分类号： H01L21/86 ,  H01L27/092 ,  H01L27/12 ,  H03K3/356 ,  H03K19/0944 ,  H03K19/0948 ,  H03L1/00 ,  H03K17/14 ,  H03K19/003 ,  H03L5/00

CPC分类号： H01L27/12 ,  H01L21/86 ,  H01L27/092 ,  H03K19/09446 ,  H03K19/09487 ,  H03K3/356 ,  Y10S257/903

摘要： A semiconductor device includes p- and n-type semiconductor layers formed on an insulating substrate and gate electrodes selectively and insulatively formed over the respective p- and n-type semiconductor layers and forming D-type MOS transistors. In this semiconductor device, the p- and n-type semiconductor layers are made in contact with each other, and negative and positive power supply terminals which are respectively set at negative and positive potentials are respectively connected to the p- and n-type semiconductor layers thereby to electrically isolate the p-type and n-type semiconductor layers from each other.

摘要翻译： 半导体器件包括在绝缘衬底上形成的p型和n型半导体层，并且在各个p型和n型半导体层上选择性地并且绝对地形成栅极，并形成D型MOS晶体管。 在该半导体器件中，使p型和n型半导体层彼此接触，分别设定为负电位和正电位的负极和正电源端分别连接到p型和n型半导体 从而将p型和n型半导体层彼此电隔离。

公开(公告)号：US4491856A

公开(公告)日：1985-01-01

申请号：US582864

申请日：1984-02-27

申请人： Hideharu Egawa ,  Yoshio Nishi ,  Kenji Maeguchi

发明人： Hideharu Egawa ,  Yoshio Nishi ,  Kenji Maeguchi

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/532 ,  H01L27/12 ,  H01L23/48 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L27/12 ,  H01L23/522 ,  H01L23/53271 ,  H01L2924/0002

摘要： A semiconductor device includes p- and n-type semiconductor layers formed on an insulating substrate and an n-type interconnection layer formed to be electrically coupled with said n-type semiconductor layer. The n-type interconnection layer is formed in contact with the p-type semiconductor layer and is set at such a potential as to apply a reverse voltage across the p-n junction between the n-type interconnection layer and p-type semiconductor layer, so as to electrically isolate the n-type interconnection layer from the p-type semiconductor layer.

摘要翻译： 半导体器件包括形成在绝缘基板上的p型和n型半导体层以及形成为与所述n型半导体层电耦合的n型互连层。 n型互连层形成为与p型半导体层接触，并且被设置为在n型互连层和p型半导体层之间的pn结上施加反向电压的电位，从而 以将n型互连层与p型半导体层电隔离。

公开(公告)号：US4280272A

公开(公告)日：1981-07-28

申请号：US85595

申请日：1979-10-17

申请人： Hideharu Egawa ,  Koji Matsuki ,  Yasoji Suzuki

发明人： Hideharu Egawa ,  Koji Matsuki ,  Yasoji Suzuki

IPC分类号： H01L21/8238 ,  H01L21/8247 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/417 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/22 ,  H01L21/265

CPC分类号： H01L21/823807 ,  H01L27/0928

摘要： A complementary semiconductor device includes P-and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.

摘要翻译： 互补半导体器件包括分别形成在半导体衬底中并具有基本相同的杂质浓度的P型和N型半导体区域。 N沟道型和P沟道型硅栅极场效应晶体管分别形成在P沟道型和N沟道型区域中。 P型和N沟道型硅栅场效应晶体管的栅电极由相同导电类型的多晶硅形成。 相同导电类型的杂质被掺杂到两个半导体区域中以提供沟道掺杂区域。

公开(公告)号：US5017994A

公开(公告)日：1991-05-21

申请号：US345358

申请日：1989-05-01

申请人： Hideharu Egawa ,  Yasoji Suzuki

发明人： Hideharu Egawa ,  Yasoji Suzuki

IPC分类号： H01L27/092 ,  H01L27/12 ,  H03K19/0948

CPC分类号： H03K19/0948 ,  H01L27/092 ,  H01L27/12

摘要： A semiconductor circuit has a power source terminal set at a positive potential, a reference potential terminal set at a reference potential, a first MOS transistor whose current path is connected between the power source terminal and an output terminal, and a second MOS transistor whose current path is connected between the output terminal and the reference potential terminal. The gates of the first and second MOS transistors are commonly connected to an input terminal. The first and second MOS transistors are respectively n- and p-channel MOS transistors.

公开(公告)号：US4975757A

公开(公告)日：1990-12-04

申请号：US111122

申请日：1987-10-20

申请人： Hideharu Egawa ,  Koji Matsuki ,  Yasoji Suzuki

发明人： Hideharu Egawa ,  Koji Matsuki ,  Yasoji Suzuki

IPC分类号： H01L21/8238 ,  H01L21/8247 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/417 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/823807 ,  H01L27/0928

摘要： A complementary semiconductor device includes P- and N-type semiconductor regions separately formed in a semiconductor substrate and having substantially the same concentration of impurities. N-and P-channel type silicon gate field effect transistors are formed in the P-and N-channel type regions, respectively. Gate electrodes of the P-and N-channel type silicon gate field effect transistors are formed by polycrystalline silicons of the same conductivity type. An impurity of the same conductivity type is doped into both the semiconductor regions to provide channel doped regions.