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44 条记录 (耗时 0.018 秒)

    Method for startup of crystal oscillator with aid of external clock injection, associated crystal oscillator and monitoring circuit therein
    1.
    发明授权
    Method for startup of crystal oscillator with aid of external clock injection, associated crystal oscillator and monitoring circuit therein 有权

    公开(公告)号：US11183971B2

    公开(公告)日：2021-11-23

    申请号：US17026275

    申请日：2020-09-20

    申请人： MEDIATEK INC.

    发明人： Chien-Wei Chen ,  Yu-Li Hsueh ,  Po-Chun Huang

    IPC分类号： H03B5/06 ,  G01R25/00 ,  H03B5/36 ,  H03B5/32

    摘要： A method for startup of a crystal oscillator (XO) with aid of external clock injection, associated XO and a monitoring circuit therein are provided. The XO includes an XO core circuit, an external oscillator, and an injection switch, where a quality factor of the external oscillator is lower than a quality factor of the XO core circuit. The method includes: utilizing the external oscillator to generate an injected signal; turning on the injection switch to make energy of the injected signal be injected into the XO core circuit, where an amplitude modulation (AM) signal is generated according to combination of the injected signal and an intrinsic oscillation signal from the XO core circuit; and controlling the external oscillator to selectively change an injection frequency of the injected signal according to the AM signal. More particularly, the injection switch is not turned off until the startup process is completed.

    Clock buffer having low power, low noise and low spur
    2.
    发明授权
    Clock buffer having low power, low noise and low spur 有权

    公开(公告)号：US10809757B2

    公开(公告)日：2020-10-20

    申请号：US16553163

    申请日：2019-08-27

    申请人： MEDIATEK INC.

    发明人： Chien-Wei Chen ,  Yu-Li Hsueh

    IPC分类号： H03K19/096 ,  G06F1/06 ,  H03K17/687 ,  H03K19/20

    摘要： The preset invention provides a clock buffer including a first circuit, a second circuit and an edge collector, wherein the first circuit is arranged to receive an input clock signal to generate a first clock signal, the second circuit is arranged to receive the input clock signal to generate a second clock signal, and the edge collector is arranged to generate an output clock signal by using a falling edge of the first clock signal and a rising edge of the second clock signal.

    QUADRATURE CLOCK GENERATING MECHANISM OF COMMUNICATION SYSTEM TRANSMITTER
    5.
    发明申请
    QUADRATURE CLOCK GENERATING MECHANISM OF COMMUNICATION SYSTEM TRANSMITTER 审中-公开

    公开(公告)号：US20180123575A1

    公开(公告)日：2018-05-03

    申请号：US15717919

    申请日：2017-09-27

    申请人： MEDIATEK INC.

    发明人： Po-Chun Huang ,  Chao-Ching Hung ,  Yu-Li Hsueh ,  Pang-Ning Chen

    IPC分类号： H03K5/15 ,  H03K21/02

    CPC分类号： H03K5/15046 ,  H03K21/026 ,  H04B1/04

    摘要： A quadrature clock generating apparatus connected to a local oscillator generating an input clock signal and an inverted input clock signal includes a fractional dividing circuit and a quadrature signal generating circuit. The fractional dividing circuit is configured for receiving the input clock signal and the inverted input clock signal, and for performing frequency-division upon the input clock signal and the inverted input clock signal to generate a frequency-divided clock signal according to a fractional dividing parameter. The quadrature signal generating circuit is configured for receiving the input clock signal, the inverted input clock signal, and the frequency-divided clock signal to generate a plurality of quadrature clock signals.

    Fractional dividing module and related calibration method
    6.
    发明授权
    Fractional dividing module and related calibration method 有权

    公开(公告)号：US09685966B2

    公开(公告)日：2017-06-20

    申请号：US14922203

    申请日：2015-10-26

    申请人： MEDIATEK INC.

    发明人： Pang-Ning Chen ,  Yu-Li Hsueh ,  Jian-Yu Ding

    IPC分类号： H03L7/197 ,  H03L7/081 ,  H03K21/02 ,  H03K23/42

    CPC分类号： H03L7/1976 ,  H03K21/023 ,  H03K23/42 ,  H03L7/081 ,  H03L7/1974

    摘要： A fractional dividing module includes an output clock generating circuit, for receiving an input clock signal and generating an output clock signal according to a first control signal, comprising a first delay unit, for delaying the input clock signal to generate a delayed input clock signal; and a selecting unit, for selecting one of the input clock signal and the delayed input clock signal to generate the output clock signal according to the first control signal; and a control circuit, for dividing the output clock signal to generate the first control signal according to a dividing control signal, wherein the dividing control is adjusted to control a frequency ratio between the output clock signal and the input clock signal.

    PHASE DETECTOR
    8.
    发明申请
    PHASE DETECTOR 有权
    相位检测器

    公开(公告)号：US20160126961A1

    公开(公告)日：2016-05-05

    申请号：US14737603

    申请日：2015-06-12

    申请人： MEDIATEK Inc.

    发明人： Pang-Ning Chen ,  Yu-Li Hsueh ,  Pi-An Wu

    IPC分类号： H03L7/089 ,  H03K3/356 ,  H03K5/156

    CPC分类号： H03L7/089 ,  H03K3/356043 ,  H03K5/1565 ,  H03L7/085

    摘要： A phase detector including a first latch and a control logic is provided. The first latch generates a first output signal and a second output signal in response to a phase difference between a first input signal and a second input signal. Each of the first and second output signals includes first phase information and second phase information of the phase difference. The control circuit generates a phase indicating signal in response to the first phase information of the phase difference. The phase indicating signal indicates a relative position between the first input signal and the second input signal.

    摘要翻译： 提供了包括第一锁存器和控制逻辑器件的相位检测器。 第一锁存器响应于第一输入信号和第二输入信号之间的相位差产生第一输出信号和第二输出信号。 第一和第二输出信号中的每一个包括相位差的第一相位信息和第二相位信息。 控制电路根据相位差的第一相位信息产生相位指示信号。 相位指示信号表示第一输入信号和第二输入信号之间的相对位置。

    Crystal oscillator and method for performing startup of crystal oscillator
    9.
    发明授权
    Crystal oscillator and method for performing startup of crystal oscillator 有权

    公开(公告)号：US12113480B2

    公开(公告)日：2024-10-08

    申请号：US18113623

    申请日：2023-02-24

    申请人： MEDIATEK INC.

    发明人： Chien-Wei Chen ,  Chao-Ching Hung ,  Yu-Li Hsueh

    IPC分类号： H03B5/36 ,  H03B5/04 ,  H03B5/12

    CPC分类号： H03B5/366 ,  H03B5/04 ,  H03B5/1265 ,  H03B2200/0094

    摘要： A crystal oscillator (XO) and a method for performing startup of the XO are provided. The XO includes a XO core circuit, an auxiliary oscillator and a frequency detection circuit, wherein the frequency detection circuit includes a resistive circuit. The frequency detection circuit generates a detection voltage according to a driving signal associated with an auxiliary signal generated by the auxiliary oscillator and a first impedance of the resistive circuit. During a first powered on phase, the auxiliary oscillator is calibrated by utilizing the XO core circuit as a reference after startup of the XO core circuit is completed, and the resistive circuit is calibrated according to the detection voltage. During a second powered on phase, a frequency of the driving signal is calibrated according to the detection voltage, and the driving signal is injected to the XO core circuit for accelerating the startup of the XO core circuit.

    FREQUENCY CALIBRATION CIRCUIT AND METHOD FOR CALIBRATING OSCILLATION FREQUENCY OF CONTROLLABLE OSCILLATOR
    10.
    发明公开
    FREQUENCY CALIBRATION CIRCUIT AND METHOD FOR CALIBRATING OSCILLATION FREQUENCY OF CONTROLLABLE OSCILLATOR 审中-公开

    公开(公告)号：US20240171161A1

    公开(公告)日：2024-05-23

    申请号：US18223537

    申请日：2023-07-18

    申请人： MEDIATEK INC.

    发明人： Chien-Wei Chen ,  Kairen Fong ,  Chao-Ching Hung ,  Yu-Li Hsueh

    IPC分类号： H03K5/01 ,  G04F10/00 ,  H03K3/037

    CPC分类号： H03K5/01 ,  G04F10/005 ,  H03K3/037

    摘要： A frequency calibration (FCAL) circuit and a method for calibrating an oscillation frequency of a controllable oscillator are provided. The FCAL circuit includes the controllable oscillator, a divider, a time-to-digital converter (TDC) and a calibration logic. The controllable oscillator generates a controllable oscillation clock according to a calibration code. The divider divides the oscillation frequency of the controllable oscillation clock by a predetermined divisor to generate a divided clock. The TDC converts a first period between first edges of a reference clock and the divided clock into a first period code and converts a second period between second edges of the reference clock and the divided clock into a second period code. The calibration logic compares the first period code and the second period code to generate a comparison result for determining whether the first period is greater or less than the second period, and accordingly controls the calibration code.