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    TIME-BASED DECISION FEEDBACK EQUALIZATION
    1.
    发明申请
    TIME-BASED DECISION FEEDBACK EQUALIZATION 审中-公开

    公开(公告)号：US20180351770A1

    公开(公告)日：2018-12-06

    申请号：US15806901

    申请日：2017-11-08

    申请人： Regents of the University of Minnesota

    发明人： Po-Wei Chiu ,  Somnath Kundu ,  Hyung-il Kim

    IPC分类号： H04L25/03 ,  H04L7/00

    CPC分类号： H04L25/03057 ,  H04L7/0041 ,  H04L7/0087 ,  H04L25/03031 ,  H04L2025/03471 ,  H04L2025/03783

    摘要： A time-based decision feedback equalizer (TB-DFE) circuit may include a voltage-to-time converter configured to convert a communication signal into a time-based signal. A timing of when an edge of the time-based signal occurs is indicative of a voltage level of the communication signal. The circuit may include a plurality of delay circuits arranged to process the time-based signal in series to generate a delay data signal. The delay circuits may adjust the timing of when the edge of the time-based signal occurs, and a corresponding time delay introduced by each of the delay circuits may be based on a respective weighting factor applied to one or more samples of an output digital signal previously generated by the TB-DFE circuit. A phase detector may compare a timing of an edge of the delay data signal with a reference clock signal and generate the output digital signal based on the comparison.

    Implicit and explicit channel sounding for beamforming
    5.
    发明授权
    Implicit and explicit channel sounding for beamforming 有权
    用于波束成形的隐式和显式的声道探测

    公开(公告)号：US09083408B2

    公开(公告)日：2015-07-14

    申请号：US13220208

    申请日：2011-08-29

    申请人： Simone Merlin ,  Didier Johannes Richard Van Nee ,  Albert Van Zelst

    发明人： Simone Merlin ,  Didier Johannes Richard Van Nee ,  Albert Van Zelst

    IPC分类号： H04B1/10 ,  H04B7/06 ,  H04L25/02 ,  H04L25/03 ,  H04L27/26

    CPC分类号： H04B7/0617 ,  H04B7/0619 ,  H04L25/0204 ,  H04L25/022 ,  H04L25/0228 ,  H04L25/03159 ,  H04L25/03343 ,  H04L27/2657 ,  H04L27/2675 ,  H04L2025/03783 ,  H04L2025/03808

    摘要： A communication device for transmitting beamformed signals using implicit channel sounding is described. The communication device includes a processor and instructions stored in memory. The communication device receives one or more sounding signals and computes a channel estimate based on the one or more sounding signals. Frequency offset compensation is applied to the channel estimate by the communication device. The communication device also computes a precoding matrix based on the channel estimate and transmits a beamformed signal using the precoding matrix. Another communication device for receiving beamformed signals using explicit channel sounding is also described. The communication device includes a processor and instructions stored in memory. The communication device receives one or more sounding signals, computes a channel estimate based on the one or more sounding signals and applies amplitude compensation to the channel estimate. The communication device also sends estimated channel data and receives a beamformed signal.

    摘要翻译： 描述了使用隐式信道探测发送波束形成信号的通信设备。 通信设备包括处理器和存储在存储器中的指令。 通信设备接收一个或多个探测信号，并且基于一个或多个探测信号来计算信道估计。 频率偏移补偿被通信装置应用于信道估计。 通信设备还基于信道估计来计算预编码矩阵，并使用预编码矩阵发送波束形成的信号。 还描述了使用显式通道探测接收波束形成信号的另一通信设备。 通信设备包括处理器和存储在存储器中的指令。 通信设备接收一个或多个探测信号，基于一个或多个探测信号计算信道估计，并对信道估计应用振幅补偿。 通信设备还发送估计的信道数据并接收波束形成的信号。

    Sign-based general zero-forcing adaptive equalizer control
    6.
    发明授权
    Sign-based general zero-forcing adaptive equalizer control 有权
    基于符号的通用强制自适应均衡器控制

    公开(公告)号：US08213494B2

    公开(公告)日：2012-07-03

    申请号：US12489356

    申请日：2009-06-22

    申请人： Yasuo Hidaka

    发明人： Yasuo Hidaka

    IPC分类号： H04L27/10

    CPC分类号： H04L25/03057 ,  H04L7/0025 ,  H04L2025/0349 ,  H04L2025/03681 ,  H04L2025/03783

    摘要： In one embodiment, a system includes one or more digital feedback equalizers (DFEs) that include one or more residual intersymbol interference (ISI) detectors, one or more column balancers, and one or more weight selectors. The residual ISI detectors produce a first output signal indicating whether the residual ISI of a received input signal has a positive sign or a negative sign. The column balancers select one of the first output signals to produce a second output signal. The weight selectors access one of the weight values. The weight value corresponds to the column balancer that produced the second output signal and the residual ISI detector that produced the first output signal, and has a magnitude that is substantially independent of the sign of the residual ISI. The weight selectors produce a third output signal based on the weight value and the sign of the residual ISI.

    摘要翻译： 在一个实施例中，系统包括一个或多个数字反馈均衡器（DFE），其包括一个或多个残余符号间干扰（ISI）检测器，一个或多个列平衡器和一个或多个权重选择器。 剩余的ISI检测器产生指示接收的输入信号的剩余ISI是否具有正号或负号的第一输出信号。 列平衡器选择第一输出信号之一以产生第二输出信号。 重量选择器访问其中一个重量值。 重量值对应于产生第二输出信号的列平衡器和产生第一输出信号的残余ISI检测器，并且具有基本上与剩余ISI的符号无关的幅度。 重量选择器基于重量值和剩余ISI的符号产生第三输出信号。

    High-performance cellular telephone receiver
    7.
    发明授权
    High-performance cellular telephone receiver 有权
    高性能手机接收机

    公开(公告)号：US08195241B2

    公开(公告)日：2012-06-05

    申请号：US12645683

    申请日：2009-12-23

    申请人： David K. Mesecher

    发明人： David K. Mesecher

    IPC分类号： H04M1/00

    CPC分类号： H04B7/086 ,  H04L25/0204 ,  H04L25/0226 ,  H04L25/03343 ,  H04L2025/03426 ,  H04L2025/03783

    摘要： A receiver includes a plurality of antennas; a plurality of front end circuits producing digital signals in response to signals received on the antennas; a beamforming unit weighting and summing the digital signals to produce a first signal; a first stage including a first plurality of modems producing first bit streams in response to components of the first signal, a first plurality of signal reconstruction units producing first signal replicas in response to the first bit streams, and a first active cancellation unit weighting the first signal replicas and subtracting the weighted first signal replicas from the first signal to produce a second signal; and a second stage including a second plurality of modems producing second bit streams in response to components of the second signal, a second plurality of signal reconstruction units producing second signal replicas in response to the second bit streams, and a second active cancellation unit weighting the second signal replicas and subtracting the weighted second signal replicas from the first signal to produce a third signal. A method implemented by the receiver is also provided.

    摘要翻译： 接收机包括多个天线; 多个前端电路响应于在天线上接收的信号产生数字信号; 波束成形单元对数字信号进行加权和求和以产生第一信号; 第一级，包括响应于第一信号的分量产生第一比特流的第一多个调制解调器，响应于第一比特流产生第一信号副本的第一多个信号重建单元，以及第一主动消除单元， 信号副本，并从第一信号中减去加权的第一信号副本以产生第二信号; 以及第二级，包括响应于第二信号的分量产生第二比特流的第二多个调制解调器，响应于第二比特流产生第二信号副本的第二多个信号重建单元，以及第二主动消除单元， 第二信号副本，并从第一信号中减去加权的第二信号副本以产生第三信号。 还提供了由接收机实现的方法。

    Adaptive equalization methods and apparatus for programmable logic devices
    8.
    发明授权
    Adaptive equalization methods and apparatus for programmable logic devices 有权
    用于可编程逻辑器件的自适应均衡方法和装置

    公开(公告)号：US08194724B1

    公开(公告)日：2012-06-05

    申请号：US12823783

    申请日：2010-06-25

    申请人： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Rakesh Patel

    发明人： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Rakesh Patel

    IPC分类号： H03H7/30 ,  H03H7/40

    CPC分类号： H04L25/03044 ,  H04L2025/03356 ,  H04L2025/03579 ,  H04L2025/03783

    摘要： A programmable logic device is provided with adaptive equalization circuitry that is programmable in one or more respects. Examples of the programmable aspects of the equalization circuitry are (1) the number of taps used, (2) whether integer or fractional spaced taps are used, (3) what starting values are used in the computation of coefficient values, (4) whether satisfactory coefficient values are computed only once or on an on-going basis, (5) whether an error signal is generated using a decision directed algorithm or using a training pattern, (6) what training pattern (if any) is used, and/or (7) the location of the sampling point in the bit period of the signal to be equalized.

    摘要翻译： 可编程逻辑器件设置有可在一个或多个方面可编程的自适应均衡电路。 均衡电路的可编程方面的示例是（1）使用的抽头数量，（2）是否使用整数或分数间隔抽头，（3）在系数值的计算中使用什么起始值，（4）是否 （5）是否使用决策导向算法或使用训练模式生成错误信号，（6）使用何种训练模式（如果有的话）和/ 或者（7）要被均衡的信号的位周期内的采样点的位置。

    CLOCK-SYNCHRONIZED METHOD FOR UNIVERSAL SERIAL BUS (USB)
    9.
    发明申请
    CLOCK-SYNCHRONIZED METHOD FOR UNIVERSAL SERIAL BUS (USB) 有权
    通用串行总线（USB）的时钟同步方法

    公开(公告)号：US20120020404A1

    公开(公告)日：2012-01-26

    申请号：US12853636

    申请日：2010-08-10

    申请人： Jiun-cheng Hsieh ,  Ying-chen Lin

    发明人： Jiun-cheng Hsieh ,  Ying-chen Lin

    IPC分类号： H04L7/00 ,  H04L27/01

    CPC分类号： H04L25/03006 ,  G06F2213/0038 ,  H04L7/10 ,  H04L2025/03783

    摘要： A clock-synchronized method for universal serial bus (USB) is described. The method includes the following steps of: (a) a transmitter sends a periodic signal to a host unit during a first time interval; (b) the host unit transmits a first equalization training sequence signal to a receiver during a second time interval to train the receiver and the transmitter continuously sends the periodic signal to the host unit; (c) a clock and data recovery device extracts the first equalization training sequence signal during the second time interval to generate a extracted clock signal and a data signal; and (d) the transmitter sends a second equalization training sequence signal to the host unit based on the extracted clock signal during the third time interval to train the host unit and the receiver and the transmitter commonly utilize the extracted clock signal as a reference clock.

    摘要翻译： 描述了通用串行总线（USB）的时钟同步方法。 该方法包括以下步骤：（a）发射机在第一时间间隔内向主机单元发送周期性信号; （b）主机单元在第二时间间隔期间向接收机发送第一均衡训练序列信号，以训练接收机，并且发射机连续向主机单元发送周期信号; （c）时钟和数据恢复装置在第二时间间隔期间提取第一均衡训练序列信号以产生提取的时钟信号和数据信号; 以及（d）发射机在第三时间间隔期间基于提取的时钟信号向主机单元发送第二均衡训练序列信号，以训练主机单元，并且接收机和发射机共同利用所提取的时钟信号作为参考时钟。

    Short Packet for Use in Beamforming
    10.
    发明申请
    Short Packet for Use in Beamforming 有权
    用于波束成形的短包

    公开(公告)号：US20110069688A1

    公开(公告)日：2011-03-24

    申请号：US12876758

    申请日：2010-09-07

    申请人： Hongyuan Zhang ,  Yong Liu ,  Hui-Ling Lou

    发明人： Hongyuan Zhang ,  Yong Liu ,  Hui-Ling Lou

    IPC分类号： H04W84/02

    CPC分类号： H04L1/0083 ,  H04B7/022 ,  H04B7/0617 ,  H04B7/0619 ,  H04J11/0053 ,  H04L25/03343 ,  H04L2025/03426 ,  H04L2025/03783 ,  H04L2025/03815 ,  H04W16/28

    摘要： A method for generating a beamforming training (BFT) unit includes generating a physical layer (PHY) preamble of the BFT unit and generating a first encoding block and a second encoding block using PHY data and MAC data, including at least one of i) using a number of padding bits in a PHY layer of the BFT unit such that the BFT unit consists of the PHY preamble, the first encoding block, and the second encoding block, and ii) generating a MAC protocol data unit (MPDU) having a length such that the BFT unit consists of the PHY preamble, the first encoding block, and the second encoding block.

    摘要翻译： 一种用于生成波束形成训练（BFT）单元的方法包括：生成BFT单元的物理层（PHY）前导码并使用PHY数据和MAC数据生成第一编码块和第二编码块，包括以下各项中的至少一个：i）使用 BFT单元的PHY层中的多个填充比特，使得BFT单元由PHY前导码，第一编码块和第二编码块组成，以及ii）生成具有长度的MAC协议数据单元（MPDU） 使得BFT单元由PHY前导码，第一编码块和第二编码块组成。