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公开(公告)号:US20240291749A1
公开(公告)日:2024-08-29
申请号:US18113240
申请日:2023-02-23
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Michael Avimelech Gandelman Milgrom , Lior Hodaya Bezen , Alex Netes , Yoav Menes , Guy Rozenberg Kunievsky , Vladimir Koushnir , Lion Levi , Eitan Zahavi
IPC: H04L45/00 , H04L45/745 , H04L47/2416 , H04L49/111
CPC classification number: H04L45/26 , H04L45/745 , H04L47/2416 , H04L49/111
Abstract: A networking device and system are described, among other things. An illustrative system is disclosed to include a switch programmed to route a received packet to an egress port based on a combination of a destination address associated with the received packet and an identification of an ingress port from which the packet was received by the switch.
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公开(公告)号:US20230239255A1
公开(公告)日:2023-07-27
申请号:US17741897
申请日:2022-05-11
Applicant: ALPHA NETWORKS INC.
Inventor: JIAN LI
IPC: H04L49/40 , H04L49/111
CPC classification number: H04L49/405 , H04L49/111
Abstract: A network switch displays a state signal of network connection ports by a combination of LEDs and includes a signal management unit, a control unit, switch members, and the LEDs. The signal management unit receives the state signal from the network connection ports and transmits data to the control unit to control each of the switch members and correspondingly output to control each of the LEDs. The state signal includes that a first state data outputs an active/inactive state via a first control signal, a second state data and a third state data output a link-down/up state and a connection speed state via a second control signal, so that the LEDs displays different states of the network connection ports based on a combination of each of the first control signal and each of the second control signal.
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公开(公告)号:US20240022524A1
公开(公告)日:2024-01-18
申请号:US18351644
申请日:2023-07-13
Applicant: Turck Holding GmbH
Inventor: Werner Bibernell , Adalbert Gabrysch
IPC: H04L49/111 , H04L49/112 , H04L49/351
CPC classification number: H04L49/111 , H04L49/112 , H04L49/351
Abstract: A station for use in a field network between at least one field device and a central unit, includes a module carrier and exchangeable pluggable modules thereon, wherein at least one of the exchangeable pluggable modules is designed as a switch module to which the at least one field device is connectable, and wherein optionally, in addition, at least one of the exchangeable pluggable modules is designed as a power supply module, the at least one switch module comprises at least one APL Ethernet port and/or at least one SPE Ethernet port for connecting the at least one field device. Further, a switch module is exchangeably pluggable in a module carrier to which one or more field devices is connectable.
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公开(公告)号:US20230353506A1
公开(公告)日:2023-11-02
申请号:US17661482
申请日:2022-04-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Aslam Khan , Khiruthigai Balasubramanian , Suhas Kumar Bharadwaj
IPC: H04L49/111 , H04L49/354 , H04L49/65 , H04L49/112 , H04L49/20
CPC classification number: H04L49/111 , H04L49/354 , H04L49/65 , H04L49/112 , H04L49/208
Abstract: An example network manager receives, from a conductor switch of a switch stack, an active configuration. The network manager determines, based on the active configuration, switch model types for a plurality of switches of the switch stack. The network manager determines, based on the switch model types and the active configuration, a number of ports of the plurality of switches of the switch stack and a current configuration of each port of each switch of the switch stack. The network manager updates a device configuration element of a network management user interface to display the current configuration of each port of each switch of the switch stack in a manner that indicates that the switch stack is a single logical switch.
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公开(公告)号:US20240154918A1
公开(公告)日:2024-05-09
申请号:US18414575
申请日:2024-01-17
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
IPC: H04L49/65 , H04L45/60 , H04L49/111
CPC classification number: H04L49/65 , H04L45/60 , H04L49/111
Abstract: A system for facilitating efficient port reconfiguration at a switch is provided. During operation, the system can identify a target port of the switch for reconfiguration based on one or more reconfiguration parameters indicating how a set of logical ports are generated from the target port. The system can disable the target port at the control plane of the switch, which disables features provided to the target port from the control plane. The control plane can provide a set of features supported by the switch at a port-level granularity for facilitating operations of the switch. The system can then configure the forwarding hardware based on the reconfiguration parameters to accommodate the set of logical ports. When the reconfiguration of the target port is complete, the system can enable a respective logical port at the control plane, which enables one or more features for the logical port from the control plane.
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公开(公告)号:US20240064116A1
公开(公告)日:2024-02-22
申请号:US17890770
申请日:2022-08-18
Applicant: Hewlett Packard Enterprise Development LP
IPC: H04L49/65 , H04L45/60 , H04L49/111
CPC classification number: H04L49/65 , H04L45/60 , H04L49/111
Abstract: A system for facilitating efficient port reconfiguration at a switch is provided. During operation, the system can identify a target port of the switch for reconfiguration based on one or more reconfiguration parameters indicating how a set of logical ports are generated from the target port. The system can disable the target port at the control plane of the switch, which disables features provided to the target port from the control plane. The control plane can provide a set of features supported by the switch at a port-level granularity for facilitating operations of the switch. The system can then configure the forwarding hardware based on the reconfiguration parameters to accommodate the set of logical ports. When the reconfiguration of the target port is complete, the system can enable a respective logical port at the control plane, which enables one or more features for the logical port from the control plane.
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公开(公告)号:US20230344532A1
公开(公告)日:2023-10-26
申请号:US17767871
申请日:2020-04-14
Applicant: Galactic Telecom Group, LLC
Inventor: James Kirunda Kakaire
IPC: H04B17/318 , H04L49/111 , H04L49/90
CPC classification number: H04B17/318 , H04L49/111 , H04L49/9068
Abstract: A Mobile Wireless Broadband Network Interface Card (MWBNIC) for networking electronic devices on a wireless broadband spectrum. The MWBNIC is built into electronic devices as a connecting modem or plugged in via external device ports such as USB. A microprocessor chip attached to a circuit board with a network packet controller coupled to a dedicated cache memory utilized to temporarily store the last N data packets from a node for networking WIFI maintains packet continuity. The network comes with protocols that control packet processing. The MWBNIC embedded packet control protocol (PCP) pushes, pops, compares and deletes packets from cache when a device is in motion. The PCP is connected to a mechanism for determining bandwidth on nodes, another mechanism for switching frequency to that of the next K-Node to connect to and a pre-determined connectivity data set that directly connects the modem in motion are means for networking broadband spectrum.
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公开(公告)号:US12126394B2
公开(公告)日:2024-10-22
申请号:US17767871
申请日:2020-04-14
Applicant: Galactic Telecom Group, LLC
Inventor: James Kirunda Kakaire
IPC: H04B17/318 , H04L49/111 , H04L49/90 , H04W36/32
CPC classification number: H04B17/318 , H04L49/111 , H04L49/9068 , H04W36/326
Abstract: A Mobile Wireless Broadband Network Interface Card (MWBNIC) for networking electronic devices on a wireless broadband spectrum. The MWBNIC is built into electronic devices as a connecting modem or plugged in via external device ports such as USB. A microprocessor chip attached to a circuit board with a network packet controller coupled to a dedicated cache memory utilized to temporarily store the last N data packets from a node for networking WIFI maintains packet continuity. The network comes with protocols that control packet processing. The MWBNIC embedded packet control protocol (PCP) pushes, pops, compares and deletes packets from cache when a device is in motion. The PCP is connected to a mechanism for determining bandwidth on nodes, another mechanism for switching frequency to that of the next K-Node to connect to and a pre-determined connectivity data set that directly connects the modem in motion are means for networking broadband spectrum.
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公开(公告)号:US20240314089A1
公开(公告)日:2024-09-19
申请号:US18474178
申请日:2023-09-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Eric Richard BORCH
IPC: H04L49/111 , H04L45/302 , H04L47/2441
CPC classification number: H04L49/111 , H04L45/306 , H04L47/2441
Abstract: A multi-node computing system. In some embodiments, the system includes: a first board and a second board. The first board may include a first switch, a second switch, a memory, and a compute element. The second board may include a first switch, a second switch, a memory, and a compute element. The first switch of the first board may be connected to the first switch of the second board and to the compute element of the first board. The first switch of the second board may be connected to the first switch of the first board and to the compute element of the second board. The second switch of the first board may be connected to the second switch of the second board and to the compute element of the first board.
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公开(公告)号:US11991095B2
公开(公告)日:2024-05-21
申请号:US17708002
申请日:2022-03-30
Applicant: Accton Technology Corporation
Inventor: Kuan-Tse Lee
IPC: H04L49/15 , H04L49/111 , H04L49/112
CPC classification number: H04L49/111 , H04L49/112 , H04L49/15
Abstract: A network system includes P upper switches, Q lower switches, and a first mapping device. Each upper switch of the P upper switches includes a plurality of upper ports. A group of upper switches selected from the P upper switches includes P1 upper switches. Each lower switch of the Q lower switches includes a plurality of upper ports. The first mapping device includes P1 upper adapter terminals coupled to a part of upper ports of the P1 upper switches, and P1 lower adapter terminals coupled to lower ports of a part of Q lower switches. The first mapping device is used for allocating a plurality of transmitting channels and receiving channels received by each upper adapter terminal to the P1 lower adapter terminals.
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