公开(公告)号：US4621315A

公开(公告)日：1986-11-04

申请号：US771919

申请日：1985-09-03

申请人： Herchel A. Vaughn ,  Joe W. Peterson

发明人： Herchel A. Vaughn ,  Joe W. Peterson

IPC分类号： H02M3/07 ,  H02M3/155

CPC分类号： H02M3/07

摘要： A charge pump which can operate at low supply voltages is provided. The charge pump recirculates charge in response to an alternating clock signal which alternates the charge across a plurality of charge storage devices. Charge recirculation is used to compensate for threshold voltage drops associated with diodes or diode-configured transistors used to implement the charge pump. As a result, voltage amplification can occur in the charge pump even for small power supply values.

摘要翻译： 提供可在低电源电压下工作的电荷泵。 电荷泵响应交替的时钟信号再循环电荷，交替时钟信号使电荷交替跨越多个电荷存储装置。 充电再循环用于补偿与用于实现电荷泵的二极管或二极管配置的晶体管相关的阈值电压降。 因此，即使对于小的电源值，电荷泵也会发生电压放大。

公开(公告)号：US4519033A

公开(公告)日：1985-05-21

申请号：US404073

申请日：1982-08-02

申请人： Herchel A. Vaughn ,  Ashok H. Someshwar

发明人： Herchel A. Vaughn ,  Ashok H. Someshwar

IPC分类号： G06F9/26 ,  G06F9/06 ,  G06F9/22

CPC分类号： G06F9/268

摘要： A control state sequencer for controlling the execution of instructions of a microprocessor uses a PLA and a ROM to detect the current control state and instruction being processed by a processing unit and to provide the next control state of the instruction to the processing unit. An initial-state PLA and initial-state ROM detect when a new instruction is to be processed by the processing unit and provides the initial clock state of the new instruction to the processing unit.

摘要翻译： 用于控制微处理器指令执行的控制状态定序器使用PLA和ROM来检测由处理单元处理的当前控制状态和指令，并将该指令的下一控制状态提供给处理单元。 初始状态PLA和初始状态ROM检测新指令将由处理单元处理并向处理单元提供新指令的初始时钟状态。

公开(公告)号：US4742480A

公开(公告)日：1988-05-03

申请号：US741914

申请日：1985-06-06

申请人： Herchel A. Vaughn ,  Kuppuswamy Raghunathan ,  Philip S. Smith

发明人： Herchel A. Vaughn ,  Kuppuswamy Raghunathan ,  Philip S. Smith

IPC分类号： G06F7/52 ,  G06F7/535 ,  G06F7/38

CPC分类号： G06F7/535 ,  G06F2207/3896 ,  G06F2207/5352 ,  G06F2207/5353

摘要： A data processor for performing a division operation requiring shifting and the counting of the number of shifts, having no dedicated counters therefor. An additional shift left path from the temporary register of the previous bit to the next bit address bus is the only extra circuitry added, which greatly simplifies the shift left circuit of the temporary register. In addition, the dedicated counter may be eliminated as a formerly idle address incrementer circuit now performs the shift left and count functions. Not only are formerly idle registers now being used for lengthy shifting and cycle counting operations, but an overall savings in chip area is recognized, since the dedicated counter is eliminated and the dedicated shifter is greatly simplified.

摘要翻译： 一种数据处理器，用于执行需要移位的划分操作和对没有专用计数器的班次数的计数。 从前一位的临时寄存器到下一位地址总线的附加的左移路径是唯一额外的电路，这大大简化了临时寄存器的左移电路。 此外，专用计数器可以被消除，因为之前的空闲地址递增器电路现在执行左移和计数功能。 以前的空闲寄存器不仅仅用于长时间的移位和周期计数操作，而是可以识别芯片面积的总体节省，因为消除了专用计数器并且极大的简化了专用移位器。

公开(公告)号：US4554467A

公开(公告)日：1985-11-19

申请号：US506959

申请日：1983-06-22

申请人： Herchel A. Vaughn

发明人： Herchel A. Vaughn

IPC分类号： H03K3/356 ,  H03K3/289 ,  H03K17/04 ,  H03K19/003

CPC分类号： H03K3/356104

摘要： A static CMOS delayed flip-flop uses only a weak P channel transistor for reinforcing a logic high at a control node while using a pair of series connected N channel transistors for reinforcing a logic low at the control node. Only a single P channel device is required because it can be made to have sufficiently low gain at a relatively small device size so that the control node can have it logic state switched by an N channel device of comparable size.

摘要翻译： 静态CMOS延迟触发器仅使用弱P沟道晶体管来加强控制节点处的逻辑高电平，同时使用一对串联连接的N沟道晶体管来增强控制节点处的逻辑低电平。 只需要一个P通道器件，因为它可以在相对较小的器件尺寸下具有足够的增益，从而控制节点可以通过相当大小的N沟道器件使其逻辑状态切换。

公开(公告)号：US4688018A

公开(公告)日：1987-08-18

申请号：US776312

申请日：1985-09-16

申请人： Herchel A. Vaughn

发明人： Herchel A. Vaughn

IPC分类号： H03M1/00 ,  H03M1/38

CPC分类号： H03M1/0872

摘要： A successive approximation analog-to-digital converter, of the type which successively compares an analog level represented by binary weighted bits with an analog signal and in response thereto generates a signal indicating whether each successive binary bit should be set or reset, includes a shaft register for counting cycles during the sampling phase and generating signals for controlling the setting and resetting of each bit. Each binary bit cell includes a latch capable of assuming first and second stable states. A first string of field-effect-transistors coupled to the latch and controlled by the shift register receives a first signal indicating that the latch should be reset. A second string of field-effect-transistors coupled to the latch and controlled by the shift register receives a signal indicating that the latch should remain in a set condition.

摘要翻译： 一种逐次逼近型模数转换器，其连续地将由二进制加权比特表示的模拟电平与模拟信号进行比较，并响应于此，产生指示每个连续的二进制位是否应被设置或复位的信号，包括轴 在采样阶段注册计数周期，并产生用于控制每个位的设置和复位的信号。 每个二进制比特单元包括能够采取第一和第二稳定状态的锁存器。 耦合到锁存器并由移位寄存器控制的第一串场效应晶体管接收指示锁存器应被复位的第一信号。 耦合到锁存器并由移位寄存器控制的第二串场效应晶体管接收指示锁存器应保持在置位状态的信号。

公开(公告)号：US4539489A

公开(公告)日：1985-09-03

申请号：US506745

申请日：1983-06-22

申请人： Herchel A. Vaughn

发明人： Herchel A. Vaughn

IPC分类号： H03K3/3565 ,  H03K3/356 ,  H03K3/295

CPC分类号： H03K3/3565

摘要： A CMOS Schmitt trigger which has two series-connected inverters uses both an input and an output signal to provide hysteresis. A pair of series-coupled transistors is coupled between a power supply terminal and a node between the two inverters. One of the transistors has a control electrode for receiving the input signal. The other of the transistors has a control electrode for receiving the output signal.

摘要翻译： 具有两个串联连接的逆变器的CMOS施密特触发器使用输入和输出信号来提供迟滞。 一对串联耦合晶体管耦合在两个逆变器之间的电源端子和节点之间。 其中一个晶体管具有用于接收输入信号的控制电极。 另一个晶体管具有用于接收输出信号的控制电极。

公开(公告)号：US4752901A

公开(公告)日：1988-06-21

申请号：US776315

申请日：1985-09-16

申请人： Herchel A. Vaughn

发明人： Herchel A. Vaughn

IPC分类号： G06F7/575 ,  G06F7/38 ,  G06F7/50 ,  H03K19/00

CPC分类号： G06F7/575

摘要： An arithmetic logic unit capable of performing AND, OR, exclusive-OR, and add functions is implemented utilizing strobed gates. An input section receives first and second inputs, each capable of assuming first and second states, and generates a first output indicating that at least one of the inputs is in a first state and a second output indicating that both inputs are in the first state. First, second and third strings of field-effect-transistors controlled by a plurality of control signals are selectively enabled respectively when at least one of the inputs is in the first state, all of the inputs are in the first state, or when only one of the inputs is in the first state. The circuit includes an output section and a circuit for generating a carry-out signal when the inputs so require.

摘要翻译： 利用选通门实现能够执行AND，OR，异或和加功能的算术逻辑单元。 输入部分接收第一和第二输入，每个输入能够采取第一和第二状态，并且产生指示输入中的至少一个处于第一状态的第一输出和指示两个输入处于第一状态的第二输出。 当输入中的至少一个处于第一状态时，所有输入都处于第一状态，或当只有一个输入时，分别选择性地使能由多个控制信号控制的第一和第三串场效应晶体管 的输入处于第一状态。 该电路包括输出部分和用于当输入如此需要时产生进位信号的电路。

公开(公告)号：US4288912A

公开(公告)日：1981-09-15

申请号：US941005

申请日：1978-09-11

申请人： Walter L. Wills ,  Herchel A. Vaughn ,  Larry L. Miller

发明人： Walter L. Wills ,  Herchel A. Vaughn ,  Larry L. Miller

IPC分类号： H01L25/07 ,  H01G4/40 ,  H01L21/603 ,  H01L25/16

CPC分类号： H01G4/40 ,  H01L2924/0002 ,  Y10S257/926 ,  Y10T29/49121

摘要： Wafers of silicon semiconductor material are stacked, bonded and severed to form a plurality of semiconductor diodes. One or more capacitor bodies are physically and electrically joined with these diodes, either by means of the capacitor bodies themselves or by means of an intermediate lead frame structure, in order to facilitate the handling and processing of the assembly as a unit.

摘要翻译： 硅半导体材料的晶片被堆叠，结合和切割以形成多个半导体二极管。 一个或多个电容器主体通过电容器本身或通过中间引线框架结构与这些二极管物理和电连接，以便于将组件作为一个单元进行处理和处理。