公开(公告)号：US5220206A

公开(公告)日：1993-06-15

申请号：US921446

申请日：1992-07-28

Applicant: Steven T. Tsang ,  Gregory T. Koker

Inventor： Steven T. Tsang ,  Gregory T. Koker

IPC: G06F1/06 ,  H03L7/089

CPC classification number: G06F1/06 ,  H03L7/0896

Abstract: Apparatus and method are provided for saving and (upon demand) restoring a control signal for a signal-controlled system. A control signal generated by or within that system is provided to a multiplexer, which normally produces that control signal. That control signal is digitized and stored by a storage device as follows. The output of the storage device is provided both to the multiplexer and to a comparator. The comparator also receives the output of the multiplexer, and compares the output of the storage device and the multiplexer. The comparator provides a signal to the storage device to increment or decrement the storage device based on whether the signal produced by the storage device is less than, or greater than or equal to, the control signal produced by the multiplexer. The multiplexer output is also provided to the signal-controlled system to provide the control signal thereto. Upon demand as indicated by a selection signal provided to the multiplexer, the stored signal from the storage device is outputted by the multiplexer, and is accordingly provided by the multiplexer to the system as the control signal. The storage device includes a resistor ladder having a plurality of evenly or unevenly incremented outputs, a selector for selecting one of those outputs to be provided to the multiplexer and to the comparator, and a counter controlled by the comparator for controlling operation of the selector.

Abstract translation: 提供装置和方法来节省和（根据需要）恢复信号控制系统的控制信号。 由该系统产生或在该系统内产生的控制信号被提供给多路复用器，其通常产生该控制信号。 该控制信号由存储装置数字化并存储如下。 存储设备的输出提供给多路复用器和比较器。 比较器还接收多路复用器的输出，并比较存储设备和多路复用器的输出。 比较器根据存储装置产生的信号是否小于或大于由多路复用器产生的控制信号，向存储装置提供信号以增加或减少存储装置。 复用器输出也被提供给信号控制系统以向其提供控制信号。 根据需要，由提供给多路复用器的选择信号指示，来自存储装置的存储信号由多路复用器输出，并且相应地由多路复用器提供给系统作为控制信号。 存储装置包括具有多个均匀或不均匀递增的输出的电阻梯，选择器，用于选择要提供给多路复用器和比较器的输出之一，以及由比较器控制的用于控制选择器的操作的计数器。

公开(公告)号：US5120990A

公开(公告)日：1992-06-09

申请号：US545887

申请日：1990-06-29

Applicant: Gregory T. Koker

Inventor： Gregory T. Koker

IPC: G06F1/06 ,  H03L7/089

CPC classification number: H03L7/0812 ,  G06F1/06 ,  H03L7/0896

Abstract: A phase detector circuit is provided for correction of operation of a synchronous delay line clock generator. The phase detector includes multiple edge detectors. The multiple edge detectors provide an override of any corrective action by the rest of the phase detector to the synchronous delay line output, notwithstanding presence or absence of any phase error of less than 360.degree., if the phase position of the delay line output signal is off by an integral multiple of 360.degree.. Multiple taps from daisy-chained or series-connected delay line elements are provided to the multiple edge detectors. The multiple edge detectors compare the edge produced by each such tap against (in the first instance) one division of divided clock signal or (for each subsequent tap) the result of the previous such comparison. In each such case, the comparison is accomplished by a not R, not S flip-flop receiving the signals to be compared. Although only two delay line elements need to be so tapped, tapping three or more such delay line elements ensures greater accuracy over a higher odd integral multiple of the clock signal. Also, even (as opposed to odd) integral multiples of the period of the clock signal are addressed by the part of the phase detector not including the edge detectors, since the phase detector receives only one of the divided clock signals. Faster correction of phase and frequency errors can be accomplished with an additional such phase detector that would be connected to the other division of the divided clock signal. This additional such phase detector would also include multiple edge detectors together receiving multiple taps from the delay line.

Abstract translation: 提供了相位检测器电路，用于校正同步延迟线时钟发生器的操作。 相位检测器包括多个边缘检测器。 如果延迟线输出信号的相位位置为0°，则多边缘检测器可以将相位检测器的其余部分对同步延迟线输出进行任何校正动作的覆盖，尽管存在或不存在小于360°的任何相位误差 360度的整数倍。 菊花链或串联连接的延迟线元件的多个抽头提供给多个边缘检测器。 多个边缘检测器将由每个这样的抽头产生的边缘与（在第一种情况下）分割时钟信号的一个分割或（对于每个后续分接头）进行比较，以前的这种比较的结果。 在每个这种情况下，通过不是R而不是S触发器来接收要比较的信号来实现比较。 尽管只需要两个延迟线元件，因此敲击三个或更多个这样的延迟线元件确保了在时钟信号的较高奇数积分倍数上的更高精度。 此外，由于相位检测器仅接收分离的时钟信号中的一个，所以由相位检测器的不包括边缘检测器的部分来寻址时钟信号周期的偶数（相对于奇数）积分倍数。 可以通过附加的这种相位检测器来实现相位和频率误差的更快校正，该相位检测器将连接到分频时钟信号的另一个分频。 这种附加的这种相位检测器还将包括多个边缘检测器，一起从延迟线接收多个抽头。

公开(公告)号：US07240129B2

公开(公告)日：2007-07-03

申请号：US10786853

申请日：2004-02-25

Applicant: John A. Hayden ,  Gregory T. Koker

Inventor： John A. Hayden ,  Gregory T. Koker

IPC: G06F3/00

CPC classification number: G06F13/34

Abstract: A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; and first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses. The DMA controller further includes a prioritizer configured to map DMA requests from different DMA requesters to the peripheral channels in response to programmable mapping information.

Abstract translation: DMA控制器包括用于处理外围设备访问总线上的DMA传输的至少一个外围DMA通道; 至少一个存储器DMA流，包括存储器目的地信道和存储器源信道，用于处理第一和第二存储器访问总线上的DMA传输; 用于计算用于DMA传输的更新的存储器地址的第一和第二地址计算单元; 以及用于分别向第一和第二存储器访问总线提供存储器地址并用于在第一和第二存储器存取总线上传送数据的第一和第二存储器管线。 DMA控制器还包括优先级化器，其被配置为响应于可编程映射信息将来自不同DMA请求者的DMA请求映射到外围信道。

公开(公告)号：US5132931A

公开(公告)日：1992-07-21

申请号：US574201

申请日：1990-08-28

Applicant: Gregory T. Koker

Inventor： Gregory T. Koker

IPC: G11C11/417 ,  G11C7/14 ,  G11C7/22 ,  G11C8/18 ,  G11C11/419

CPC classification number: G11C7/22 ,  G11C7/14 ,  G11C8/18

Abstract: A sense enable timing circuit for addressing data locations in a static random access memory (RAM) array provides a plurality of memory cells formed into a dummy row and a dummy column that is connected to a memory cell at a far end opposite an X-decoder input of said dummy row. The dummy row and column are constructed in conjunction on the same semiconductor chip with a RAM array comprising a plurality of memory cells formed into rows and columns. The dummy column connects to a dummy word line of the dummy row and includes dummy bit lines. Each of the dummy word and bit lines are separate from the word lines and bit lines of the array. The dummy word line is addressed at a time synchronized with the addressing of the array word lines. The occurrence of a predetermined voltage change on at least one of the dummy bit lines, carrying a signal of at least one memory cell of the dummy column, is determined in response to the addressing of the dummy word line. In response to this determination, the sensing of array bit line signal is enabled. The signal carried by the dummy bit line may be generated by a plurality of adjacent memory cells.

Abstract translation: 用于寻址静态随机存取存储器（RAM）阵列中的数据位置的感测使能定时电路提供形成为虚拟行的多个存储单元和连接到与X解码器相对的远端的存储单元的虚拟列 所述虚拟行的输入。 虚拟行和列在相同的半导体芯片上结合构造，具有包括形成行和列的多个存储单元的RAM阵列。 虚拟列连接到虚拟行的虚拟字线并且包括虚拟位线。 每个虚拟字和位线与阵列的字线和位线分开。 在与阵列字线的寻址同步的位置处寻址伪字线。 响应于虚拟字线的寻址来确定承载虚拟列的至少一个存储单元的信号的至少一个虚拟位线上的预定电压变化的发生。 响应于该确定，启用阵列位线信号的感测。 由虚位线携带的信号可以由多个相邻的存储单元产生。

公开(公告)号：US07702862B2

公开(公告)日：2010-04-20

申请号：US11704143

申请日：2007-02-08

Applicant: Moinul I. Syed ,  Richard A. Gentile ,  Gregory T. Koker

Inventor： Moinul I. Syed ,  Richard A. Gentile ,  Gregory T. Koker

IPC: G06F12/00 ,  G06F11/34

CPC classification number: G06F11/348 ,  G06F11/3409 ,  G06F11/349 ,  G06F2201/88

Abstract: A processing system includes a processing circuit having one or more buses, a memory interface unit to control access by the processing circuit to a memory, and a metrics module. The metrics module includes one or more metrics registers and a metrics controller to monitor one or more operations selected from memory interface unit operations and bus operations, and to store metrics information corresponding to the monitored operations in the metrics registers. The monitored operations can include memory access operations, arbitration operations, bus operations, and the like. The metrics information can be analyzed to provide a basis for improving performance of a program that is executed on the processing system.

Abstract translation: 处理系统包括具有一个或多个总线的处理电路，用于控制处理电路对存储器的访问的存储器接口单元以及度量模块。 度量模块包括一个或多个度量寄存器和度量控制器，用于监视从存储器接口单元操作和总线操作中选择的一个或多个操作，以及将与所监视的操作相对应的度量信息存储在度量寄存器中。 所监视的操作可以包括存储器访问操作，仲裁操作，总线操作等。 可以分析度量信息以提供用于提高在处理系统上执行的程序的性能的基础。

公开(公告)号：US20080195825A1

公开(公告)日：2008-08-14

申请号：US11704143

申请日：2007-02-08

Applicant: Moinul I. Syed ,  Richard A. Gentile ,  Gregory T. Koker

Inventor： Moinul I. Syed ,  Richard A. Gentile ,  Gregory T. Koker

IPC: G06F12/00

CPC classification number: G06F11/348 ,  G06F11/3409 ,  G06F11/349 ,  G06F2201/88

Abstract: A processing system includes a processing circuit having one or more buses, a memory interface unit to control access by the processing circuit to a memory, and a metrics module. The metrics module includes one or more metrics registers and a metrics controller to monitor one or more operations selected from memory interface unit operations and bus operations, and to store metrics information corresponding to the monitored operations in the metrics registers. The monitored operations can include memory access operations, arbitration operations, bus operations, and the like. The metrics information can be analyzed to provide a basis for improving performance of a program that is executed on the processing system.

Abstract translation: 处理系统包括具有一个或多个总线的处理电路，用于控制处理电路对存储器的访问的存储器接口单元以及度量模块。 度量模块包括一个或多个度量寄存器和度量控制器，用于监视从存储器接口单元操作和总线操作中选择的一个或多个操作，以及将与所监视的操作相对应的度量信息存储在度量寄存器中。 所监视的操作可以包括存储器访问操作，仲裁操作，总线操作等。 可以分析度量信息以提供用于提高在处理系统上执行的程序的性能的基础。

公开(公告)号：US6118301A

公开(公告)日：2000-09-12

申请号：US84670

申请日：1998-05-26

Applicant: Jaspreet Singh ,  Gregory T. Koker ,  Mark R. Newman

Inventor： Jaspreet Singh ,  Gregory T. Koker ,  Mark R. Newman

IPC: H03K17/10 ,  G06F13/40 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/02

CPC classification number: H03K19/00315 ,  G06F13/4072

Abstract: An input/output driver circuit which provides a buffer interface between a functional digital circuit and a common bus for other digital circuits achieves high levels of voltage tolerance and compliance, while requiring only two power supply pins, by using two PMOS switching transistors between the circuit's output line and an output power supply terminal, rather than only one. To turn the transistors OFF, the output power supply voltage is applied to the gate of one of them and the output line voltage to the gate of the other. This assures that at least one of the transistors is fully OFF when desired, whether or not the output line voltage exceeds the output power supply level.

Abstract translation: 在功能数字电路和其他数字电路的公共总线之间提供缓冲器接口的输入/输出驱动器电路通过在电路的两个PMOS开关晶体管之间使用两个PMOS开关晶体管来实现高水平的电压容限和兼容性，同时仅需要两个电源引脚 输出线和输出电源端子，而不仅仅是一个。 为了关闭晶体管，输出电源电压被施加到其中一个的栅极和另一个的栅极的输出线电压。 这确保了当需要时至少一个晶体管完全关断，无论输出线电压是否超过输出电源电平。

公开(公告)号：US5341033A

公开(公告)日：1994-08-23

申请号：US980247

申请日：1992-11-23

Applicant: Gregory T. Koker

Inventor： Gregory T. Koker

IPC: H03K3/013 ,  H03K3/3565 ,  H03K3/295

CPC classification number: H03K3/3565 ,  H03K3/013

Abstract: An input buffer circuit incorporates variable hysteresis levels to protect against unintended changes of output state in response to glitches in the input signal. The circuit is used in connection with input signals that alternate between LO and HI input states with known minimum periods between alternations. The switching threshold hysteresis for reverting back to a prior output state is boosted during the period following an input signal transition, with the boosted hysteresis removed following a delay period that is no greater than the minimum period between successive input signal transitions. Numerous circuit designs may be used to implement the varying hysteresis levels.

Abstract translation: 输入缓冲电路包含可变滞后电平，以防止输入信号中的毛刺响应输出状态的意外变化。 该电路与输入信号结合使用，该输入信号在LO和HI输入状态之间交替，在交替之间具有已知的最小周期。 在输入信号转换之后的周期期间，恢复到先前输出状态的开关阈值滞后被提升，其中在不大于连续输入信号转换之间的最小周期的延迟周期之后消除升压滞后。 可以使用许多电路设计来实现变化的滞后电平。