公开(公告)号：US06677813B2

公开(公告)日：2004-01-13

申请号：US10186728

申请日：2002-07-01

申请人： Hermann Ruckerbauer ,  Andre Schäfer

发明人： Hermann Ruckerbauer ,  Andre Schäfer

IPC分类号： H03B100

CPC分类号： G11C7/225 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1087

摘要： An integrated circuit for receiving a clock signal is described and has a clock input and a receiver circuit. A clock signal can be applied to the clock input. A filter circuit is provided, whose input is connected to the clock input for the purpose of filtering out a frequency and/or a frequency range of the clock signal. An output of the filter circuit, which output produces the filtered clock signal, is connected to the receiver circuit for the purpose of transferring the filtered clock signal to the integrated circuit for processing.

摘要翻译： 描述用于接收时钟信号的集成电路，并具有时钟输入和接收器电路。 时钟信号可以应用于时钟输入。 提供一个滤波器电路，其输入端连接到时钟输入端，用于滤除时钟信号的频率和/或频率范围。 输出产生滤波后的时钟信号的滤波电路的输出连接到接收机电路，目的是将滤波的时钟信号传送到集成电路进行处理。

公开(公告)号：US07523250B2

公开(公告)日：2009-04-21

申请号：US11509092

申请日：2006-08-24

申请人： Paul Wallner ,  Andre Schäfer ,  Peter Gregorius

发明人： Paul Wallner ,  Andre Schäfer ,  Peter Gregorius

IPC分类号： G06F11/14 ,  G06F13/28

CPC分类号： G11C8/12 ,  G11C7/1051 ,  G11C2207/107

摘要： A semiconductor memory system includes a semiconductor memory chip in which data, command, and address signals are transmitted serially between a memory controller and the semiconductor memory chip in signal frames in correspondence with a predetermined protocol. In a receive signal path within the semiconductor memory chip, a frame decoder for decoding the signal frames is arranged following a receiving interface device, and between the frame decoder and a memory core, an intermediate storage device is arranged which has a cell array including a multiplicity of memory cells, and an addressing and selector circuit to which address signals decoded by the frame decoder from command and/or write signal frames supplied by the memory controller are applied, for addressing the cell array and for selecting the write data to be written into the cell array and to be read out of the cell array.

摘要翻译： 半导体存储器系统包括半导体存储器芯片，其中数据，命令和地址信号在与预定协议相对应的信号帧中的存储器控​​制器和半导体存储器芯片之间串行发送。 在半导体存储器芯片内的接收信号路径中，用于对信号帧进行解码的帧解码器被布置在接收接口设备之后，并且在帧解码器和存储器核心之间，布置中间存储设备，其具有包括单元阵列 多个存储器单元，以及寻址和选择器电路，由帧解码器从由存储器控制器提供的命令和/或写入信号帧解码的地址信号被应用于寻址单元阵列并用于选择要写入的写入数据 进入单元阵列并从单元阵列中读出。

公开(公告)号：US07139206B2

公开(公告)日：2006-11-21

申请号：US11031740

申请日：2005-01-07

申请人： Andre Schäfer

发明人： Andre Schäfer

IPC分类号： G11C7/02

CPC分类号： H03F3/45475 ,  G11C11/4074 ,  H03F1/26

摘要： A memory component comprises a memory cell array, signal inputs, input amplifiers connected to respective ones of the signal inputs, for receiving, amplifying and outputting data, address or control signals, a data, address or control signal generator for the memory cell array, a first supply network for supplying power to the input amplifiers and a second supply network for supplying power to the data, address or control signal generator, wherein the first supply network and the second supply network do not have a direct connection.

摘要翻译： 存储器组件包括存储单元阵列，信号输入，连接到相应信号输入端的输入放大器，用于接收，放大和输出数据，地址或控制信号，用于存储单元阵列的数据，地址或控制信号发生器， 用于向输入放大器供电的第一供电网络和用于向数据，地址或控制信号发生器供电的第二供电网络，其中第一供电网络和第二供电网络不具有直接连接。

公开(公告)号：US06476658B2

公开(公告)日：2002-11-05

申请号：US09847673

申请日：2001-05-02

申请人： Andre Schäfer

发明人： Andre Schäfer

IPC分类号： H03K508

CPC分类号： G11C5/063

摘要： The circuit configuration, in particular a DRAM element, has a protection device for suppressing the formation and/or emission of a reflection signal caused by a received supply input signal. An active signal matching device is provided, with which it is possible to prevent the formation of a reflection signal by using the input signal.

摘要翻译： 电路结构，特别是DRAM元件，具有用于抑制由接收的电源输入信号引起的反射信号的形成和/或发射的保护装置。 提供了一种有源信号匹配装置，可以通过使用输入信号来防止形成反射信号。

公开(公告)号：US08418610B2

公开(公告)日：2013-04-16

申请号：US12609735

申请日：2009-10-30

申请人： Andre Schäfer ,  Friedrich Steger ,  Frank Wagner

发明人： Andre Schäfer ,  Friedrich Steger ,  Frank Wagner

IPC分类号： B41F5/00

CPC分类号： B41F13/0008 ,  B41F13/008 ,  B41F13/085

摘要： A printing unit of a printing press, such as a web press constructed as a periodical printing press, having at least one printing couple, wherein the printing couple or each printing couple comprises a form cylinder, a transfer cylinder, an inking unit, and preferably a dampening unit. A drive motor is associated with at least one printing couple, and drives the form cylinder or the transfer cylinder of a respective printing couple. In accordance with the invention, a flywheel mass is associated with at least one drive motor which drives the form cylinder or the transfer cylinder of the respective printing couple, where the flywheel mass is connected to the rotor of the respective drive motor in a torsionally rigid manner.

摘要翻译： 印刷机的印刷单元，例如作为周期性印刷机构成的网状印刷机，具有至少一个印刷对，其中印刷对或每个印刷对包括成型滚筒，传送滚筒，上墨单元，优选地 一个阻尼单元。 驱动马达与至少一个打印对相关联，并驱动相应打印对的形状滚筒或传送滚筒。 根据本发明，飞轮物质与至少一个驱动马达相关联，所述至少一个驱动马达驱动相应打印对的形状滚筒或传送滚筒，其中飞轮质量块以相对于驱动马达的转子连接到扭转刚性 方式。

公开(公告)号：US06636097B2

公开(公告)日：2003-10-21

申请号：US10186650

申请日：2002-07-01

申请人： Hermann Ruckerbauer ,  Andre Schäfer

发明人： Hermann Ruckerbauer ,  Andre Schäfer

IPC分类号： G06G764

CPC分类号： G11C7/1084 ,  G11C7/1078 ,  H03K5/08 ,  H03K5/125

摘要： The invention relates to a method and to an input circuit for evaluating a data item in a data signal at an input of a memory component. The data signal is integrated between a start time and an end time that are specified by a control signal. An integration period between the start time and the end time depends on the frequency of the data signal. The data item is assigned a logic data value based on the result of the integration. The input circuit has a comparator device, an integration device and a switching device. The data signal is first integrated in order to obtain an integration value. The comparator device compares the integration value with a prescribed threshold value. A logic data value is assigned to the data item based on the result of the comparison.

摘要翻译： 本发明涉及一种用于评估存储器组件的输入端的数据信号中的数据项的方法和输入电路。 数据信号被集成在由控制信号指定的开始时间和结束时间之间。 开始时间和结束时间之间的积分周期取决于数据信号的频率。 基于积分的结果为数据项分配逻辑数据值。 输入电路具有比较器装置，集成装置和开关装置。 首先整合数据信号以获得积分值。 比较器装置将积分值与规定的阈值进行比较。 基于比较的结果将逻辑数据值分配给数据项。

公开(公告)号：US06525977B2

公开(公告)日：2003-02-25

申请号：US09910749

申请日：2001-07-23

申请人： Andre Schäfer

发明人： Andre Schäfer

IPC分类号： G11C702

CPC分类号： G11C7/10 ,  G11C11/4093 ,  H03K5/1252 ,  H04L25/08

摘要： A circuit configuration prevents a transfer of interference signals present on an input line to a processing section. Electrical input signals are evaluated in an analysis circuit which is connected in parallel with the actual reception circuit in a protection device. If an interference signal is present, a transfer circuit is controlled such that a transfer to the processing section is prevented.

公开(公告)号：US07009420B2

公开(公告)日：2006-03-07

申请号：US10815541

申请日：2004-04-01

申请人： Andre Schäfer

发明人： Andre Schäfer

IPC分类号： H03K17/16

CPC分类号： G11C7/225 ,  G11C7/1078 ,  G11C7/1084 ,  H04L25/0298

摘要： An input circuit for receiving a signal at an input on an integrated circuit, particularly a DRAM circuit, and for assessing the signal with respect to a reference voltage is provided. One embodiment provides a termination circuit for setting a termination voltage, wherein the termination circuit includes a first resistor and a second resistor connected in series between a high voltage potential and a low voltage potential, the termination voltage being tapped between the first and second resistors, a first voltage-dependent resistor element having a first resistance gradient connected in parallel with the first resistor and a second voltage-dependent resistor element having a second resistance gradient connected in parallel with the second resistor, wherein the resistance values of the first and second resistor elements are controlled by a control voltage to set the termination voltage.

摘要翻译： 提供了一种用于在集成电路，特别是DRAM电路的输入处接收信号并用于相对于参考电压评估信号的输入电路。 一个实施例提供了一种用于设置终端电压的终端电路，其中终端电路包括串联连接在高电压电位和低电压电位之间的第一电阻器和第二电阻器，终端电压被抽头在第一和第二电阻器之间， 具有与第一电阻并联连接的第一电阻梯度的第一电压相关电阻器元件和具有与第二电阻器并联连接的第二电阻梯度的第二电压相关电阻器元件，其中第一和第二电阻器的电阻值 元件由控制电压控制以设定终止电压。

公开(公告)号：US06819625B2

公开(公告)日：2004-11-16

申请号：US10266353

申请日：2002-10-07

申请人： Hermann Ruckerbauer ,  Andre Schäfer

发明人： Hermann Ruckerbauer ,  Andre Schäfer

IPC分类号： G11C700

CPC分类号： G11C7/222 ,  G11C5/025 ,  G11C7/22

摘要： A memory device has a memory module, a controller, a data bus for connecting the controller and the memory module, a read clock generator, and a read clock bus for connecting the read clock generator, the memory module, and the Controller. The data bus read data from the memory module or writes data into the memory module. The read clock generator is disposed in the memory module, so that the data bus and the read clock bus are substantially symmetric, and generate a read clock for transferring data from the memory module to the controller. The data bus and the read clock bus are configured with respect to each other such that substantially no time delay between read data on the data bus and the read clock on the read clock bus exists at the controller.

摘要翻译： 存储器件具有存储器模块，控制器，用于连接控制器和存储器模块的数据总线，读时钟发生器和用于连接读时钟发生器，存储器模块和控制器的读时钟总线。 数据总线从存储器模块读取数据或将数据写入存储器模块。 读时钟发生器设置在存储器模块中，使得数据总线和读时钟总线基本对称，并且生成用于将数据从存储器模块传送到控制器的读时钟。 数据总线和读时钟总线相对于彼此配置，使得在控制器上存在数据总线上的读数据和读时钟总线上的读时钟之间基本上没有时间延迟。

公开(公告)号：US06804160B2

公开(公告)日：2004-10-12

申请号：US10290365

申请日：2002-11-07

申请人： Andre Schäfer ,  Andrea Zuckerstätter

发明人： Andre Schäfer ,  Andrea Zuckerstätter

IPC分类号： G11C700

CPC分类号： G11C5/14

摘要： A memory device includes a memory module, a control unit and a bus connected to the memory module and the control unit. In an accessing operation of the memory module via bus, the control unit applies a first command which causes high power consumption in the memory module, to the memory module via part of the bus only.

摘要翻译： 存储器件包括存储器模块，控制单元和连接到存储器模块和控制单元的总线。 在通过总线对存储器模块进行访问操作时，控制单元仅通过部分总线将存储模块中的高功耗的第一命令应用于存储器模块。