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1.发明授权Controlled leakage CMOS decoupling capacitor for application specific integrated circuit libraries 失效用于专用集成电路库的可控泄漏CMOS去耦电容公开(公告)号：US07098523B2
公开(公告)日：2006-08-29
申请号：US10732950
申请日：2003-12-11
IPC分类号： H01L29/00
CPC分类号： H01L27/0682
摘要： A decoupling capacitor includes a fixed resistance in series with the capacitor, the resistance formed by contacts connecting a polysilicon layer to metal and a diffusion layer to metal; the contacts being of location and quantity sufficient for limiting defect current while allowing the capacitor to function at high frequency. N pairs of contacts in at least two sets of contacts are separated by a distance K sufficient to achieve a leakage limiting resistance of R and a bandwidth limiting resistance of R/2.
摘要翻译： 去耦电容器包括与电容器串联的固定电阻，由将多晶硅层连接到金属的触点和向金属扩散层形成的电阻; 触点的位置和数量足以限制缺陷电流，同时允许电容器以高频率工作。 至少两组触点中的N对触点被分开足够的距离K，以实现R的泄漏限制电阻和R / 2的带宽限制电阻。
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公开(公告)号：US06362653B1
公开(公告)日：2002-03-26
申请号：US09777286
申请日：2001-02-06
IPC分类号： H03K1716
CPC分类号： H03K19/00315
摘要： A high voltage tolerant receiver that matches a voltage drop across an NFET pass-gate at the input to the receiver with a voltage drop across a semiconductor device, formatted as a diode, and connected between an input stage and an input stage voltage supply source.
摘要翻译： 一个高耐压接收器，其匹配在接收器的输入端上的NFET通过栅极上的电压降，并且跨接半导体器件的压降，被格式化为二极管，并连接在输入级和输入级电压源之间。
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公开(公告)号：US06335637B1
公开(公告)日：2002-01-01
申请号：US09541196
申请日：2000-04-03
IPC分类号： H03K190175
CPC分类号： H03K19/00315 , H03K19/09429
摘要： The protection circuit of the present invention addresses the problem of indeterminate logic levels caused by loss of one of the power supplies in a two-power-supply CMOS integrated circuit. The circuit of the present invention replaces the typical scheme of power supply sequencing to fix the problem. The circuit disclosed herein detects the state of the core voltage and disables the output drivers when the core voltage is detected as being off. The disabled drivers are put into a high impedance state, thereby eliminating the potential for damage and eliminating the need for power supply sequencing. The invention also protects against the sudden loss of the integrated circuit core voltage, VDD, power supply during normal operation.
摘要翻译： 本发明的保护电路解决了由两电源CMOS集成电路中的一个电源的损耗引起的不确定的逻辑电平的问题。 本发明的电路取代了电源排序的典型方案来解决问题。 本文所公开的电路检测核心电压的状态，并且当核心电压被检测为关闭时，禁用输出驱动器。 禁用的驱动器处于高阻抗状态，从而消除了损坏的可能性，并消除了对电源排序的需要。 本发明还可以防止在正常工作期间集成电路核心电压VDD，电源的突然损失。
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4.发明授权ASIC architecture for active-compensation of a programmable impedance I/O 失效用于可编程阻抗I / O的有源补偿的ASIC架构公开(公告)号：US06922074B2
公开(公告)日：2005-07-26
申请号：US10072165
申请日：2002-02-07
IPC分类号： G06F3/00 , H03K19/00 , H03K19/0175 , H03K17/16 , H03K19/003
CPC分类号： H03K19/0005
摘要： A method of, and a circuit for, impedance control. The method comprises the steps of providing an input/output cell having a controllable input/output impedance, providing a reference cell including a node having a variable voltage, and comparing the voltage of the node to a reference voltage. The voltage of the node is adjusted during a defined period and according to a defined procedure, and during that defined period, a digital signal is generated. That digital signal is transmitted to the input/output cell to adjust the input/output impedance. Preferably, the circuit is embodied as a digital controller designed as a synthesized core or macro. The advantage of this implementation is that it never has to be redesigned in future technologies. The digital controller may be carried over to future technologies in the form of VHDL code, which is pure logic and independent of technology.
摘要翻译： 阻抗控制的方法和电路。 该方法包括以下步骤：提供具有可控输入/输出阻抗的输入/输出单元，提供包括具有可变电压的节点的参考单元，并将该节点的电压与参考电压进行比较。 节点的电压在定义的时间段内并根据定义的过程进行调整，并且在该定义的周期期间，产生数字信号。 该数字信号被传输到输入/输出单元以调整输入/输出阻抗。 优选地，电路被实现为被设计为合成核心或宏的数字控制器。 这种实现的优点在于，它从未在未来的技术中重新设计。 数字控制器可以以VHDL代码的形式转移到未来的技术中，这是纯逻辑和独立于技术的。
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公开(公告)号：US06262599B1
公开(公告)日：2001-07-17
申请号：US09544132
申请日：2000-04-06
IPC分类号： H03K190175
CPC分类号： H03K19/09429 , H03K19/018521
摘要： A low power CMOS bidirectional I/O buffer that translates low voltage core logic level signals into the higher voltage logic level signals. A first predrive stage is provided, comprising buffers (e.g., CMOS inverters) for tuning and balancing the circuit and the core signal combining circuit of a second predrive stage, thereby enabling IC designers to reduce the size of transistors in the level-shifting stage and providing more flexibility in the tuning of the predrive circuitry to synchronize or balance the logical transitions of the complementary transistors of the output driving stage. The invention provides a faster balanced level-shifting output buffer which enables higher frequency operation.
摘要翻译： 低功耗CMOS双向I / O缓冲器，可将低电压核心逻辑电平信号转换为较高电压逻辑电平信号。 提供了第一预驱动级，包括用于调谐和平衡第二预驱动级的电路和核心信号组合电路的缓冲器（例如，CMOS反相器），从而使得IC设计者能够在电平移位级中减小晶体管的尺寸， 在预调制电路的调谐中提供更大的灵活性以同步或平衡输出驱动级的互补晶体管的逻辑转换。 本发明提供了一种更快的平衡电平转换输出缓冲器，其实现更高频率的操作。
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6.发明授权Method, circuit library and computer program product for implementing enhanced performance and reduced leakage current for ASIC designs 失效方法，电路库和计算机程序产品，用于实现ASIC设计的增强性能和减少漏电流公开(公告)号：US07257781B2
公开(公告)日：2007-08-14
申请号：US10760502
申请日：2004-01-20
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method, apparatus and computer program product are provided for implementing application specific integrated circuit (ASIC) designs having high performance and reduced leakage current. Standard voltage threshold (SVT) circuits in a SVT circuit library are identified. For each SVT circuit, each SVT PFET is replaced with a low voltage threshold (LVT) PFET to provide a hybrid alternate voltage threshold (AVT) circuit. Then the AVT circuits are saved in an alternate voltage threshold circuit library. The AVT circuit library provides enhanced performance as compared to the SVT circuit library without the high leakage current resulting from a LVT circuit library.
摘要翻译： 提供了一种用于实现具有高性能和降低的漏电流的专用集成电路（ASIC）设计的方法，装置和计算机程序产品。 识别SVT电路库中的标准电压阈值（SVT）电路。 对于每个SVT电路，每个SVT PFET被替换为低电压阈值（LVT）PFET，以提供混合交替电压阈值（AVT）电路。 然后将AVT电路保存在交流电压阈值电路库中。 与SVT电路库相比，AVT电路库提供了更高的性能，而没有LVT电路库产生的高漏电流。
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公开(公告)号：US06493257B1
公开(公告)日：2002-12-10
申请号：US10108687
申请日：2002-03-27
IPC分类号： G11C11412
CPC分类号： G11C14/00
摘要： A state saving circuit and method for using the same. The circuit comprises a first latch powered by an uninterrupted power supply, wherein the first latch includes a first pair of cross coupled inverters for storing data, and includes an input cut-off control for isolating the data in the first pair of cross coupled inverters; a second latch coupled to an output of the first latch and powered by an interruptible power supply, wherein the second latch includes a second pair of cross coupled inverters and a clock input for latching the data from the first latch to the second latch; and wherein an interruption of power to the second latch results in a state being saved in the first latch.
摘要翻译： 一种状态保存电路及其使用方法。 电路包括由不间断电源供电的第一锁存器，其中第一锁存器包括用于存储数据的第一对交叉耦合的反相器，并且包括用于隔离第一对交叉耦合的反相器中的数据的输入截止控制; 耦合到所述第一锁存器的输出并由可中断电源供电的第二锁存器，其中所述第二锁存器包括第二对交叉耦合的反相器和用于将所述数据从所述第一锁存器锁存到所述第二锁存器的时钟输入; 并且其中对所述第二锁存器的电力中断导致在所述第一锁存器中保存状态。
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8.发明授权Using thick-oxide CMOS devices to interface high voltage integrated circuits 失效使用厚氧化物CMOS器件来连接高压集成电路公开(公告)号：US06181193B2
公开(公告)日：2001-01-30
申请号：US09415862
申请日：1999-10-08
IPC分类号： H03K301
CPC分类号： H03K19/00315
摘要： A high voltage tolerant CMOS input/output interface circuit. In this circuit, a process feature called “dual-gate” or “thick-oxide” process is used on any devices that will be exposed to high voltage. The thick-oxide devices have a larger capacitance and lower bandwidth, and therefore, preferably, they are only used where exposure to high voltage can cause damage. The remaining devices on the interface circuit may all use a standard process with the thinner oxide, allowing the I/O and the core IC to run at maximum speed. The circuit design topology also limits the number of devices that are exposed to high voltage. Preferably, the protection scheme is broken down into two parts: the driver and receiver.
摘要翻译： 高耐压CMOS输入/输出接口电路。 在该电路中，在将被暴露于高电压的任何器件上使用称为“双栅极”或“厚氧化物”工艺的工艺特征。 厚氧化物器件具有较大的电容和较低的带宽，因此，优选地，它们仅在暴露于高电压可能导致损坏的情况下使用。 接口电路上的其余器件都可以使用较薄氧化物的标准工艺，允许I / O和核心IC以最大速度运行。 电路设计拓扑也限制了暴露于高电压的器件数量。 优选地，保护方案分为两部分：驱动器和接收器。
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9.发明授权Using thick-oxide CMOS devices to interface high voltage integrated circuits 失效使用厚氧化物CMOS器件来连接高压集成电路公开(公告)号：US06504418B1
公开(公告)日：2003-01-07
申请号：US09660423
申请日：2000-09-12
IPC分类号： H03K508
CPC分类号： H03K19/00315
摘要： A high voltage tolerant CMOS input/output interface circuit. In this circuit, a process feature called “dual-gate” or “thick-oxide” process is used on any devices that will be exposed to high voltage. The thick-oxide devices have a larger capacitance and lower bandwidth, and therefore, preferably, they are only used where exposure to high voltage can cause damage. The remaining devices on the interface circuit may all use a standard process with the thinner oxide, allowing the I/O and the core IC to run at maximum speed. The circuit design topology also limits the number of devices that are exposed to high voltage. Preferably, the protection scheme is broken down into two parts: the driver and receiver.
摘要翻译： 高耐压CMOS输入/输出接口电路。 在该电路中，在将被暴露于高电压的任何器件上使用称为“双栅极”或“厚氧化物”工艺的工艺特征。 厚氧化物器件具有较大的电容和较低的带宽，因此，优选地，它们仅在暴露于高电压可能导致损坏的情况下使用。 接口电路上的其余器件都可以使用较薄氧化物的标准工艺，允许I / O和核心IC以最大速度运行。 电路设计拓扑也限制了暴露于高电压的器件数量。 优选地，保护方案分为两部分：驱动器和接收器。
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公开(公告)号：US06441670B1
公开(公告)日：2002-08-27
申请号：US09930413
申请日：2001-08-15
IPC分类号： H03K508
CPC分类号： H03K5/08 , H03K19/00315
摘要： Receiver circuit providing interface between a legacy system sourcing logic signals including high logic level signals at first voltage levels to semiconductor IC devices operating at second voltage levels, wherein the first voltage levels are greater than the second voltage levels. The receiver circuit comprises: a pass gate device receiving the input voltages including high level logic signals at first logic levels and translating the high logic level signals to an intermediate voltage level for output at a first circuit node, the intermediate voltage level being less than the first voltage level; a first inverter device for receiving the translated voltages at the intermediate voltage levels and inverting the voltages for output at a second circuit node, whereby high input logic level voltages are pulled down at the second node and low input logic level voltages are pulled up at the second node; a circuit element in series with the first inverter device for connecting the first inverter device to a voltage supply source that provides pulled up signals at the second voltage levels in response to low logic level input voltages; and, a circuit responsive to pulled down voltage at the second node for deactivating the first circuit element to thereby prevent leakage current to ground through the first inverter device. Stable switching of voltages is achieved at the second node in a manner that eliminates leakage current between the voltage supply source providing pulled up signals at the second voltage levels and the receiver input.
摘要翻译： 接收器电路提供传统系统之间的接口，逻辑信号包括在第一电压电平处的高逻辑电平信号到在第二电压电平工作的半导体IC器件，其中第一电压电平大于第二电压电平。 接收器电路包括：通过栅极器件，其接收包括处于第一逻辑电平的高电平逻辑信号的输入电压，并将高逻辑电平信号转换成中间电压电平以在第一电路节点处输出，所述中间电压电平小于 第一电压电平; 第一逆变器装置，用于接收处于中间电压电平的转换电压并使第二电路节点处的输出电压反相，从而在第二节点向下拉高输入逻辑电平电压，并在第二节点处将低输入逻辑电平电压拉高 第二节点 与所述第一逆变器装置串联的电路元件，用于将所述第一逆变器装置连接到电压源，所述电压源响应于低逻辑电平输入电压而以所述第二电压电平提供上拉信号; 以及响应于第二节点处的下拉电压的电路，用于停用第一电路元件，从而防止通过第一逆变器装置接地的漏电流。 在第二节点处实现稳定的电压切换，以消除在第二电压电平提供上拉信号的电压源和接收器输入之间的泄漏电流。
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