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公开(公告)号：US20230352415A1
公开(公告)日：2023-11-02
申请号：US17730765
申请日：2022-04-27
发明人： Thomas Dungan
IPC分类号： H01L23/538 , H01L25/065 , H01L23/00 , H01L25/00
CPC分类号： H01L23/5386 , H01L25/0652 , H01L24/83 , H01L25/50 , H01L24/16 , H01L24/32 , H01L2224/32145 , H01L2224/16225 , H01L2924/1437 , H01L2924/1436 , H01L2924/1431 , H01L2224/83895 , H01L2924/37001
摘要： A device may include a host substrate with two or more circuit regions, one or more first stacks electrically connected to the circuit regions, and one or more second stacks providing electrical connections between the circuit regions. At least some of the second stacks may include an insulator wafer bonded to a die, where the die is bonded to at least one of the circuit regions. At least one of the second stacks may include a power distribution pathway to provide the electrical power to at least one of the circuit regions, which may include includes electrically-conductive vias through the insulator wafer and the die or capacitors in the die. Further, the die of at least one of the one or more second stacks may include electrical pathways to provide electrical connections between at least two of the two or more circuit regions.
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公开(公告)号：US20230245973A1
公开(公告)日：2023-08-03
申请号：US17588504
申请日：2022-01-31
IPC分类号： H01L23/538 , H01L21/48 , H01L23/552
CPC分类号： H01L23/5386 , H01L21/4857 , H01L23/552 , H01L24/16
摘要： An electrical device for transporting electrical signals, wherein the electrical device comprises a plurality of signal wires each configured for transporting electrical signals, and a plurality of shield wires being staggered with respect to each other and each being configured for shielding signal wires with respect to each other, wherein each shield wire is arranged between a respective pair of signal wires and extends only along a subsection of each signal wire of the respective pair.
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公开(公告)号：US20220384407A1
公开(公告)日：2022-12-01
申请号：US17331196
申请日：2021-05-26
发明人： Thomas Edward DUNGAN
IPC分类号： H01L25/18 , H01L25/065 , H01L23/00 , H01L23/367 , H01L23/48 , H01L23/538 , H01L25/00
摘要： A memory system includes a memory stack including a number of memory dies interconnected via copper bonding, a logic die coupled to the memory stack via a copper bonding. The memory system further includes a buffer die extended to provide the copper bonding between the logic die and the memory stack and a silicon carrier layer bonded to the memory stack and the logic die.
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公开(公告)号：US20240096745A1
公开(公告)日：2024-03-21
申请号：US17946883
申请日：2022-09-16
CPC分类号： H01L23/46 , H01L23/481 , H01L24/05 , H01L24/08 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/80 , H01L24/83 , H01L2224/05647 , H01L2224/08145 , H01L2224/131 , H01L2224/29186 , H01L2224/2929 , H01L2224/29324 , H01L2224/29339 , H01L2224/29347 , H01L2224/29393 , H01L2224/29439 , H01L2224/29447 , H01L2224/32225 , H01L2224/80379 , H01L2224/80895 , H01L2224/80896 , H01L2224/8385
摘要： A manufacturing method of a chip package, performing a coupling of first and second interconnecting layers between one or more top dies and one or more bottom dies via hybrid copper bonding; depositing a material to at least partially cover the second interconnecting layer; thinning a second surface of the one or more top dies, wherein both the one or more top dies and the material define a continuous surface; coupling a first surface of a support die to the second surface of at least one of the one or more top dies; thinning a second surface of at least one of the one or more bottom dies; and coupling the second surface of at least one of the one or more bottom dies to a plurality of microbumps.
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公开(公告)号：US20240036263A1
公开(公告)日：2024-02-01
申请号：US17876867
申请日：2022-07-29
发明人： Nourhan Eid , Shiyun Lin , Naser Dalvand , Vivek Raghunathan
IPC分类号： G02B6/30
CPC分类号： G02B6/305
摘要： An optical coupler configured to couple light along a propagation direction is disclosed. The optical coupler includes a lower area. The lower area includes a waveguide including a first end, a second end, and an inversely tapered portion. The optical coupler includes an intermediary area arranged over, in a vertical direction, the lower area. The intermediary area includes two or more intermediary elements. The optical coupler includes an upper area arranged over the intermediary area. The upper area includes one or more upper elements.
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公开(公告)号：US11538790B2
公开(公告)日：2022-12-27
申请号：US17491072
申请日：2021-09-30
IPC分类号： H01L23/50 , H01L25/065 , H01L23/538 , H01L25/00
摘要： A semiconductor package includes an interposer, a number of a first integrated circuit (IC) dies, one or more second IC dies, and one or more dummy dies. The first IC dies, the second IC dies and the dummy dies are implemented on the interposer. The dummy dies are configured to enable routing of pins of the first IC dies to selected circuits of the second IC dies while conforming to predefined routing rules.
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公开(公告)号：US20220302080A1
公开(公告)日：2022-09-22
申请号：US17491072
申请日：2021-09-30
IPC分类号： H01L25/065 , H01L25/00 , H01L23/538
摘要： A semiconductor package includes an interposer, a number of a first integrated circuit (IC) dies, one or more second IC dies, and one or more dummy dies. The first IC dies, the second IC dies and the dummy dies are implemented on the interposer. The dummy dies are configured to enable routing of pins of the first IC dies to selected circuits of the second IC dies while conforming to predefined routing rules.
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公开(公告)号：US11784785B2
公开(公告)日：2023-10-10
申请号：US17728470
申请日：2022-04-25
发明人： Jeffrey Grundvig
CPC分类号： H04L7/06
摘要： Novel tools and techniques are provided for implementing synchronization signal (“Sync Mark”) detection using multi-frequency sinusoidal (“MFS”) signal-based filtering. In various embodiments, a computing system may detect a location of a Sync Mark within a data signal, by using MFS signal-based filtering and a sliding window comprising successive search windows each having a bit length corresponding to a bit length of the Sync Mark to identify a portion of the data signal having a magnitude indicative of the Sync Mark. The computing system may refine the location of the Sync Mark within the data signal, by performing a phase measurement on the identified portion of the data signal having the magnitude indicative of the Sync Mark to identify a sub-portion of the identified portion of the data signal, the identified sub-portion having a phase indicative of the Sync Mark, the phase measurement being performed based on the MFS signal-based filtering.
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公开(公告)号：US20230290703A1
公开(公告)日：2023-09-14
申请号：US17876488
申请日：2022-07-28
发明人： Thomas Edward Dungan
IPC分类号： H01L23/373 , H01L25/18 , H01L23/498 , H05K1/18 , H01L21/48 , H01L25/00
CPC分类号： H01L23/3735 , H01L25/18 , H01L23/49822 , H05K1/18 , H01L21/4857 , H01L25/50 , H01L25/0652
摘要： Copper-connected glass modules on a glass board are provided. An apparatus includes one or more dies, an interposer formed of a first material, the interposer coupled to the one or more silicon dies, the interposer comprising an interconnection layer formed on one side of the interposer, wherein the interconnection layer includes a plurality of copper interconnects, and a substrate comprising a top layer, glass core, and a bottom layer, wherein the interconnection layer of the interposer and the top layer of the substrate are copper bonded.
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公开(公告)号：US20230251442A1
公开(公告)日：2023-08-10
申请号：US17848225
申请日：2022-06-23
CPC分类号： G02B6/4292 , G02B6/3853 , G02B6/423
摘要： A coupled optic system is disclosed. The coupled optic system includes an optic system. The optic system includes a frame, one or more interface lenses, a lid, and one or more frame alignment surfaces. The coupled optic system further includes an optical connector. The optical connector includes one or more connector lenses, an optical connector holder, and one or more holder alignment surfaces. The optic system is configured to be removably couplable to the optical connector, and the one or more frame alignment surfaces are configured to be removably couplable to the one or more holder alignment surfaces.
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