公开(公告)号：US06822926B2

公开(公告)日：2004-11-23

申请号：US10197643

申请日：2002-07-18

申请人： Masahiro Kanai ,  Teruhiko Kamei

发明人： Masahiro Kanai ,  Teruhiko Kamei

IPC分类号： H10L29788

CPC分类号： G11C16/3427 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/7923

摘要： A non-volatile semiconductor memory device having a memory cell array region in which a plurality of memory cells, each having first and second MONOS memory cells controlled by a word gate and control gates, are arranged in first and second directions. The memory cell array region has a plurality of sector regions divided in the second direction. Each of a plurality of control gate drivers is capable of setting a potential of first and second control gates in the corresponding sector region independently of other sector regions. A plurality of switching elements which select connection/disconnection are formed at connections between a plurality of main bit lines and a plurality of sub bit lines.

摘要翻译： 具有存储单元阵列区域的非易失性半导体存储器件，其中在第一和第二方向布置有由字门控制的第一和第二MONOS存储单元和控制栅极的多个存储单元。 存储单元阵列区域具有沿第二方向分割的多个扇区区域。 多个控制栅极驱动器中的每一个能够独立于其它扇区区域来设置相应扇区中的第一和第二控制栅极的电位。 选择连接/断开的多个开关元件形成在多个主位线与多个子位线之间的连接处。

公开(公告)号：US06812518B2

公开(公告)日：2004-11-02

申请号：US10285540

申请日：2002-11-01

申请人： Takashi Miida

发明人： Takashi Miida

IPC分类号： H10L29788

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11543 ,  H01L29/66825 ,  H01L29/7887

摘要： A multiple-bit cell transistor includes a P type silicon substrate, agate insulation layer, a pair of N type source/drain regions, a pair of tunnel insulation layers, and a pair of floating gates. The silicon substrate is formed with a projection while the floating gates each are positioned on one of opposite side walls of the projection. Inter-polycrystalline insulation layers each are formed on one of the floating gates. A control gate faces the top of the projection via the gate insulation layer. An N type region is formed on each side of the projection and contacts the source/drain region adjoining it. The cell transistor lowers a required write voltage, broadens a current window, and enhances resistance to inter-band tunneling.

摘要翻译： 多位单元晶体管包括P型硅衬底，玛瑙绝缘层，一对N型源极/漏极区，一对隧道绝缘层和一对浮动栅极。 硅衬底形成有突起，而浮栅各自位于突起的相对侧壁中的一个上。 多晶硅绝缘层各自形成在一个浮动栅极上。 控制门通过栅极绝缘层面向突起的顶部。 N型区域形成在突起的每一侧上，并与其邻接的源极/漏极区域接触。 单元晶体管降低了所需的写入电压，拓宽了当前窗口，并增强了对带内隧道效应的阻力。