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公开(公告)号:US11902068B2
公开(公告)日:2024-02-13
申请号:US17517795
申请日:2021-11-03
发明人: Dae Won Lee , Dong Wook Roh , Byeong Woo Kang , Yong Ho Seok , Yu Jin Noh , Bong Hoe Kim
IPC分类号: H04W84/12 , H04B7/0413 , H04L27/14 , H03M5/12 , H04L27/00 , H04L25/49 , H04W28/06 , H04L27/26 , H04L1/00 , H04L27/22 , H04L27/227 , H04L27/156 , H04Q1/46 , H04L27/233 , H04L27/148 , H04L27/144 , H04N21/426
CPC分类号: H04L27/261 , H04B7/0413 , H04L1/0041 , H04L1/0061 , H04L27/22 , H04L27/2613 , H04W84/12 , H03M5/12 , H04L25/4904 , H04L27/14 , H04L27/144 , H04L27/148 , H04L27/1563 , H04L27/2273 , H04L27/2331 , H04L27/2332 , H04L27/2647 , H04L2027/0028 , H04N21/426 , H04Q1/46 , H04W28/06
摘要: A method of transmitting a Physical Layer Convergence Procedure (PLCP) frame in a Very High Throughput (VHT) Wireless Local Area Network (WLAN) system includes generating a MAC Protocol Data Unit (MPDU) to be transmitted to a destination station (STA), generating a PLCP Protocol Data Unit (PPDU) by adding a PLCP header, including an L-SIG field containing control information for a legacy STA and a VHT-SIG field containing control information for a VHT STA, to the MPDU, and transmitting the PPDU to the destination STA. A constellation applied to some of Orthogonal Frequency Division Multiplex (OFDM) symbols of the VHT-SIG field is obtained by rotating a constellation applied to an OFDM symbol of the L-SIG field.
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公开(公告)号:US20230308325A1
公开(公告)日:2023-09-28
申请号:US18323449
申请日:2023-05-25
发明人: Gongzheng ZHANG , Tianhang YU , Chen XU , Rong LI , Jun WANG , Wen TONG
IPC分类号: H04L27/156 , H04L1/00
CPC分类号: H04L27/1563 , H04L1/0057
摘要: A data transmission method includes obtaining a data stream. The data stream includes a plurality of bit groups. The method also includes modulating the data stream into a modulated symbol stream according to a modulation rule, and generating a modulated signal based on the modulated symbol stream. The modulated symbol stream includes a plurality of modulated symbol. The modulation rule includes determining, in a symbol period of one modulated symbol based on a value of a first bit group, a zero time point corresponding to the first bit group. The zero time point is a zero crossing point of the modulated signal in the symbol period. The first bit group includes at least one bit. The first bit group is one of the plurality of bit groups. The method further includes sending the modulated signal.
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公开(公告)号:US11637663B2
公开(公告)日:2023-04-25
申请号:US17456843
申请日:2021-11-29
IPC分类号: H04L5/00 , H04L27/156 , H04L27/26 , H04W52/52
摘要: Methods, systems and device for achieving synchronization in an orthogonal time frequency space (OTFS) signal receiver are described. An exemplary signal reception technique includes receiving an OTFS modulated wireless signal comprising pilot signal transmissions interspersed with data transmissions, calculating autocorrelation of the wireless signal using the wireless signal and a delayed version of the wireless signal that is delayed by a pre-determined delay, thereby generating an autocorrelation output, processing the autocorrelation filter through a moving average filter to produce a fine timing signal. Another exemplary signal reception technique includes receiving an OTFS modulated wireless signal comprising pilot signal transmissions interspersed with data transmissions, performing an initial automatic gain correction of the received OTFS wireless signal by peak detection and using clipping information, performing coarse automatic gain correction on results of a received and initial automatic gain control (AGC)-corrected signal.
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公开(公告)号:US11246188B2
公开(公告)日:2022-02-08
申请号:US16798462
申请日:2020-02-24
发明人: Tomohiro Yamaguchi
IPC分类号: H04W88/08 , H04L27/144 , H04L27/156 , H04W72/04
摘要: A wireless communication apparatus performs communication for which a receiving timing and a transmitting timing are defined by using time slots. The wireless communication apparatus includes a control circuitry configured to control the wireless communication apparatus. The control circuitry includes a decoding circuitry configured to start a decoding process, on data received in a first time slot, immediately after a start of a second time slot subsequent to the first time slot. When a result of the decoding process is information requesting the wireless communication apparatus to perform transmission, the control circuitry is configured to perform a transmission preparation process from an end of the decoding process to a start of a third time slot subsequent to the second time slot, within a period of the second time slot for enabling the wireless communication apparatus to perform transmission.
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公开(公告)号:US11233683B2
公开(公告)日:2022-01-25
申请号:US16850378
申请日:2020-04-16
发明人: Philip J. Agar , Alison Cooper
IPC分类号: H04L27/14 , H04L27/156 , H04L27/10 , H04L27/144
摘要: A method for processing an electrical signal comprises receiving an electrical signal comprising a frequency modulated signal encoding digital data; sampling a first portion of the electrical signal to obtain a plurality of samples to obtain a first sample set; determining an index value from the first sample set by assigning a value to each sample in the first sample set based upon an amplitude of the sample; comparing the determined index value with a plurality of predetermined index values to identify a first output value from a plurality of predetermined output values, each of the predetermined index values corresponding to one of the plurality of predetermined output values; and outputting an indication of the output value. Each of the predetermined output values indicates a respective frequency modulation encoded value and the first output value indicates a frequency modulation encoded value within the first portion of the electrical signal.
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公开(公告)号:US11063794B2
公开(公告)日:2021-07-13
申请号:US16833177
申请日:2020-03-27
摘要: A continuous-time sampler has series-connected delay lines with intermediate output taps between the delay lines. Signal from an output tap can be buffered by an optional voltage buffer for performance. A corresponding controlled switch is provided with each output tap to connect the output tap to an output of the continuous-time sampler. The delay lines store a continuous-time input signal waveform within the propagation delays. Controlling the switches corresponding to the output taps with pulses that match the propagation delays can yield a same input signal value at the output. The continuous-time sampler effectively “holds” or provides the input signal value at the output for further processing without requiring switched-capacitor circuits that sample the input signal value onto some capacitor. In some cases, the continuous-time sampler can be a recursively-connected delay line. The continuous-time sampler can be used as the front end sampler in a variety of analog-to-digital converters.
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公开(公告)号:US11057256B1
公开(公告)日:2021-07-06
申请号:US17062726
申请日:2020-10-05
摘要: A receiver-implemented method is for measuring a periodically modulated signal. The method includes applying a received periodically modulated signal to a mixer of a receiver, the periodically modulated signal not synchronized with the receiver, and tuning a local oscillator (LO) of the mixer using an estimate of actual carrier frequency and an estimate of an arbitrary waveform generator (AWG) sampling rate to obtain a digitized intermediate frequency (IF) signal. The method further includes applying a short time Fourier transform (STFT) to the digitized IF signal, extracting a carrier frequency offset and a AWG sampling rate offset based on the applied STFT, compensating for the carrier frequency offset, and applying a digital correction to the STFT to compensate for the AWG sampling rate offset. Compensating for the carrier frequency offset may include retuning the LO to obtain a new digitized IF signal to which the digital correction is applied.
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公开(公告)号:US20200235966A1
公开(公告)日:2020-07-23
申请号:US16269532
申请日:2019-02-06
发明人: Jian WANG , Yong WANG , Haijiao FAN , Reza Alavi , Abdelaziz CHIHOUB , Esha JOHN , Saeed AGHTAR
IPC分类号: H04L27/156 , H04L27/144 , H04W52/02 , H04W56/00 , H04B17/318
摘要: Apparatuses and methods related to digital mobile radio (DMR) with enhanced transceiver are disclosed herein. The transceiver detects waveforms of signals received by a digital mobile station radio (MS). By detecting whether the waveforms of the signals, the transceiver allows a digital baseband processor of the MS to remain in a sleep state while the signals are being detected by the DMR, thereby reducing an amount of power used while the signals are being detected.
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公开(公告)号:US10700903B2
公开(公告)日:2020-06-30
申请号:US16337526
申请日:2017-07-29
发明人: Wenli Shu , Congyin Wang , Qiyi Zhao
IPC分类号: H04L27/144 , H04L27/156 , H04J3/04 , H02J7/02 , H04B5/00 , H04L27/148
摘要: A circuit structure for efficiently demodulating an FSK signal in a wireless charging device, comprising a data sampling module, a period point counting module, a data distribution module, and a period point processing module. An input terminal of the period point counting module is connected to an output terminal of the data sampling module; an input terminal of the data distribution module is connected to an output terminal of the period point counting module; and an input terminal of the period point processing module is connected to an output terminal of the data distribution module.
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公开(公告)号:US20190268193A1
公开(公告)日:2019-08-29
申请号:US15904139
申请日:2018-02-23
申请人: Invecas, Inc.
IPC分类号: H04L27/156 , H03K9/08 , H03K5/003
摘要: A receiver for demodulating a pulse width modulated (“PWM”) signal, comprises: a voltage level shifter for shifting the PWM signal to predefined transistor voltage levels; a half-rate PWM decoder for receiving the shifted PWM signal; and a 2-bit-to-N-bit deserializer. The half-rate PWM decoder comprises a first decoder core, a second decoder core, a controller, and a sampler and retiming circuit. The first decoder core and the second decoder core are configured to decode alternating periods of the shifted PWM signal. The controller is coupled to the first decoder core, the second decoder core, the sampler and retiming circuit. The retiming circuit is configured to receive clock signals from the controller and to output half-rate even data from the first decoder core and half-rate odd data from the second decoder core. Outputs of the retiming circuit and an output of the controller are coupled to inputs of the deserializer.
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